PR533
USB NFC integrated reader solution
Rev. 3.6 — 27 October 2014
206436
Product short data sheet
COMPANY PUBLIC
1. General description
The PR5331C3HN is a highly integrated transceiver module for contactless reader/writer
communication at 13.56 MHz.
A dedicated ROM code is implemented to handle different RF protocols by an integrated
microcontroller. The system host controller communicates with the PR5331C3HN by
using the USB or the HSU link.
The protocol between the host controller and the PR5331C3HN, on top of this physical
link is the CCID protocol.
1.1 RF protocols
PR5331C3HN supports the PCD mode for FeliCa (212 kbps and 424 kbps),
ISO/IEC14443 Type A and B (from 106 kbps to 848 kbps), MIFARE (106 kbps), B' cards
(106 kbps), picoPass tag (106 kbps) and Innovision Jewel cards (106 kbps)
The Initiator passive mode (from 106 kbps to 424 kbps) can be supported through the
PC/SC transparent mode.
1.2 Interfaces
The PR5331C3HN supports a USB 2.0 full speed interface (bus powered or host powered
mode).
Alternatively to the USB interface, a High Speed UART (from 9600b up to 1.2 Mb) can be
used to connect the PR533 to a host.
The PR5331C3HN has also a master I
2
C-bus interface that allows to connect one of the
following peripherals:
•
An external EEPROM: in this case the PR5331C3HN is configured as master and is
able to communicate with external EEPROM (address A0h) which can store
configuration data like PID, UID and RF parameters. When a USB host interface is
used, these parameters are retrieved from the EEPROM at startup of the device
•
A TDA8029 contact smart card reader
1.3 Standards compliancy
PR5331C3HN offers commands in order for applications to be compliant with “EMV
Contactless Communication Protocol Specification V2.0.1”.
PR5331C3HN supports RF protocols ISO/IEC 14443A and B such as compliancy with
Smart eID standard can be achieved at application level.
NXP Semiconductors
PR533
USB NFC integrated reader solution
Support of USB 2.0 full speed, interoperable with USB 3.0 hubs.
The PR533C3HN in PCD mode is compliant with EMV contactless specification V2.0.1.
1.4 Supported operating systems
•
•
•
•
•
•
Microsoft Windows 2000
Microsoft Windows XP (32 and 64 bits)
Microsoft Windows 2003 Server (32 and 64 bits)
Microsoft Windows 2008 Server (32 and 64 bits)
Microsoft Windows Vista (32 and 64 bits)
Microsoft Windows 7 (32 and 64 bits)
The PR533 is supported by the following OS through the PCSC-Lite driver:
•
•
•
•
•
GNU/Linux using libusb 1.0.x and later
Mac OS Leopard (1.5.6 and newer)
Mac OS Snow Leopard (1.6.X)
Solaris
FreeBSD
2. Features and benefits
USB 2.0 full speed host interface and CCID protocol support
Integrated microcontroller implements high-level RF protocols
Buffered output drivers to connect an antenna with minimum number of external
components
Integrated RF level detector
Integrated data mode detector
Supports ISO/IEC 14443A Reader/Writer mode up to 848 kbit/s
Supports ISO/IEC 14443B Reader/Writer mode up to 848 kbit/s
Supports contactless communication according to the FeliCa protocol at 212 kbit/s and
424 kbit/s
Supports MIFARE encryption
Typical operating distance in Read/Write mode for communication to
ISO/IEC 14443A/MIFARE, ISO/IEC 14443B or FeliCa cards up to 50 mm depending
on antenna size and tuning
I
2
C-bus master interface allows to connect an external I
2
C EEPROM for configuration
data storage or to control a TDA8029 contact smart card reader
Low-power modes
Hard power-down mode
Soft power-down mode
Only one external oscillator required (27.12 MHz Crystal oscillator)
Power modes
USB bus power mode
2.5 V to 3.6 V power supply operating range in non-USB bus power mode
PR533_SDS
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.6 — 27 October 2014
206436
2 of 36
NXP Semiconductors
PR533
USB NFC integrated reader solution
Dedicated I/O ports for external device control
3. Quick reference data
Table 1.
Symbol
V
BUS
Quick reference data
Parameter
bus supply voltage
(non-USB mode);
V
BUS
= V
DDD;
V
SSD
= 0 V
V
DDA
V
DDD
V
DD(TVDD)
V
DD(PVDD)
V
DD(SVDD)
analog supply voltage
digital supply voltage
TVDD supply voltage
PVDD supply voltage
SVDD supply voltage
V
SSA
= V
SSD
= V
SS(PVSS)
=
V
SS(TVSS)
= 0 V; reserved for
future use
maximum load current (USB
mode); measured on V
BUS
maximum inrush current lim-
itation; at power-up
(curlimoff = 0)
I
pd
power-down current
hard power-down;
RF level detector off
soft power-down; RF level
detector on
I
CCSL
I
DDD
I
DD(SVDD)
I
DDA
I
DD(TVDD)
P
tot
T
amb
[1]
Conditions
Min
4.02
2.5
[1]
[1]
[1]
Typ
5
3.3
3.3
3.3
3.3
-
Max
5.25
3.6
3.6
3.6
3.6
3.6
V
DDD
Unit
V
V
V
V
V
V
V
V
DDA
= V
DDD
= V
DD(TVDD)
=
V
DD(PVDD)
; V
SSA
= V
SSD
=
V
SS(PVSS)
= V
SS(TVSS)
= 0 V
2.5
2.5
2.5
1.6
V
DDD
0.1 -
I
BUS
bus supply current
150
100
mA
mA
V
DDA
= V
DDD
= V
DD(TVDD)
= V
DD(PVDD)
= 3 V; not powered from USB
10
30
-
[1]
A
A
A
mA
mA
mA
mA
W
C
suspended low-power
device supply current
digital supply current
SVDD supply current
analog supply current
TVDD supply current
total power dissipation
ambient temperature
RF level detector on, (with-
out resistor on DP/DM)
RF level detector on,
V
DD(SVDD)
switch off
V
DDS
= 3 V
RF level detector on
during RF transmission;
V
DD(TVDD)
= 3 V
T
amb
=
30
to +85
C
-
15
-
6
60
-
-
250
-
30
-
100
0.55
+85
-
-
-
-
-
30
V
DDD
, V
DDA
and V
DD(TVDD)
must always be at the same supply voltage.
PR533_SDS
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.6 — 27 October 2014
206436
3 of 36
NXP Semiconductors
PR533
USB NFC integrated reader solution
4. Ordering information
Table 2.
Ordering information
Package
Name
PR5331C3HN/C360
[1][2][3]
PR5331C3HN/C370
[1][2][3]
[1]
[2]
[3]
Type number
Description
Version
SOT618-1
HVQFN40 plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6
6
0.85 mm
60 or 70 refers to the ROM code version described in the User Manual. For differences of romcode versions refer to the release note of
the product.
Refer to
Section 14.4 “Licenses”.
MSL 2 (Moisture Sensitivity Level).
5. Block diagram
The following block diagram describes hardware blocks controlled by PR5331C3HN
firmware or which can be accessible for data transaction by a host baseband.
RSTPD_N
RSTOUT_N
DVDD
P70_IRQ
AVSS
VBUS
DVSS
SUPPLY
SUPERVISOR
REGULATOR
3.3 V
SVDD
SWITCH
PCR
SVDD
SIGIN
SIGOUT
P34
OSCIN
OSCOUT
27 MHz OSC
AND
FRAC N
PLL
48 MHz
DELATT
USB
DEVICE
I0
MATX
I1
80C51 CPU
44 k ROM
1.2 k BYTES RAM
SDA
P50_SCL
I
2
C
MASTER
NFC
ANALOG
FRONT END
AND
CLUART
TVDD
AVDD
RX
VMID
TX1
TVSS
TX2
PVDD
P30 P31
P32_INT0
GPIOs
P33_INT0
P35
aaa-000043
Fig 1.
Block diagram
PR533_SDS
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.6 — 27 October 2014
206436
4 of 36
NXP Semiconductors
PR533
USB NFC integrated reader solution
6. Pinning information
6.1 Pinning
38 RSTPD_N
31 P33_INT1
30 P32_INT0
29 P31
28 P30
27 DELATT
26 PVDD
25 DP
24 DM
23 DVSS
22 RSTOUT_N
21 P70_IRQ
AVSS 11
AUX1 12
AUX2 13
DVSS 14
OSCIN 15
OSCOUT 16
I0 17
I1 18
TESTEN 19
P35 20
aaa-000044
terminal 1
index area
DVSS
LOADMOD
TVSS1
TX1
TVDD
TX2
TVSS2
AVDD
VMID
1
2
3
4
5
6
7
8
9
PR533
RX 10
Transparent top view
Fig 2. Pin configuration for HVQFN 40 (SOT618-1)
6.2 Pin description
Table 3.
Symbol
DVSS
LOADMOD
TVSS1
TX1
TVDD
TX2
TVSS2
AVDD
VMID
RX
AVSS
AUX1
AUX2
DVSS
PR533_SDS
PR533 pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Type Pad ref
voltage
G
O
G
O
P
O
G
P
P
I
G
O
O
G
DVDD
DVDD
AVDD
AVDD
TVDD
TVDD
DVDD
Description
digital ground
load modulation output provides digital signal for FeliCa and MIFARE card
operating mode
transmitter ground: supplies the output stage of TX1
transmitter 1: transmits modulated 13.56 MHz energy carrier
transmitter power supply: supplies the output stage of TX1 and TX2
transmitter 2: delivers the modulated 13.56 MHz energy carrier
transmitter ground: supplies the output stage of TX2
analog power supply
internal reference voltage: This pin delivers the internal reference voltage.
receiver input: Input pin for the reception signal, which is the load modulated
13.56 MHz energy carrier from the antenna circuit
analog ground
auxiliary output 1: This pin delivers analog and digital test signals
auxiliary output 2: This pin delivers analog and digital test signals
digital ground
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.6 — 27 October 2014
206436
32 P50_SCL
35 SIGOUT
39 DVDD
37 SVDD
40 VBUS
36 SIGIN
33 SDA
34 P34
5 of 36
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