CBTD3861
10-bit level shifting bus switch with output enable
Rev. 2 — 21 November 2011
Product data sheet
1. General description
The CBTD3861 provides ten bits of high-speed TTL-compatible bus switching. The low
ON resistance of the switch allows connections to be made with minimal propagation
delay.
The CBTD3861 device is organized as one 10-bit bus switches with one output enable
(OE) input. When OE is LOW, the switch is on and port A is connected to the B port. When
OE is HIGH, each switch is disabled.
The CBTD3861 is characterized for operation from
40 C
to +85
C.
2. Features and benefits
Designed to be used in 5 V to 3.3 V level shifting applications with internal diode
5
switch connection between two ports
TTL-compatible control input levels
Multiple package options
Latch-up protection exceeds 100 mA per JESD78
ESD protection:
HBM JESD22-A114F exceeds 2000 V
CDM JESD22-C101C exceeds 1000 V
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
CBTD3861PW
40 C
to +85
C
CBTD3861DK
40 C
to +85
C
Name
TSSOP24
SSOP24
[1]
Description
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
plastic shrink small outline package; 24 leads;
body width 3.9 mm; lead pitch 0.635 mm
Version
SOT355-1
SOT556-1
SOT815-1
Type number
CBTD3861BQ
40 C
to +85
C
DHVQFN24 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 24 terminals;
body 3.5
5.5
0.85 mm
[1]
Also known as QSOP24 package
NXP Semiconductors
CBTD3861
10-bit level shifting bus switch with output enable
4. Functional diagram
2
22
A1
B1
A10
OE
11
23
13
B10
001aam471
Fig 1.
Logic diagram
5. Pinning information
5.1 Pinning
CBTD3861
n.c.
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
24 V
CC
23 OE
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 B8
14 B9
13 B10
001aam477
CBTD3861
n.c.
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
24 V
CC
23 OE
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 B8
14 B9
13 B10
001aam478
A9 10
A10 11
GND 12
A9 10
A10 11
GND 12
Fig 2.
Pin configuration for TSSOP24 (SOT355-1)
Fig 3.
Pin configuration for SSOP24 (SOT556-1)
CBTD3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 21 November 2011
2 of 16
NXP Semiconductors
CBTD3861
10-bit level shifting bus switch with output enable
CBTD3861
terminal 1
index area
A1
A2
A3
A4
A5
A6
A7
A8
2
3
4
5
6
7
8
9
GND
(1)
GND 12
B10 13
24 V
CC
23 OE
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 B8
14 B9
n.c.
1
A9 10
A10 11
001aam479
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input.
Fig 4.
Pin configuration for DHVQFN24 (SOT815-1)
5.2 Pin description
Table 2.
Symbol
n.c.
A1 to A10
GND
B1 to B10
OE
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9, 10, 11
12
23
24
Description
not connected
data input/output (A port)
ground (0 V)
output enable input (active LOW)
positive supply voltage
22, 21, 20, 19, 18, 17, 16, 15, 14, 13 data input/output (B port)
6. Functional description
Table 3.
Input
OE
L
H
[1]
Function selection
[1]
Input/output
An, Bn
An = Bn
Z
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
CBTD3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 21 November 2011
3 of 16
NXP Semiconductors
CBTD3861
10-bit level shifting bus switch with output enable
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
T
amb
=
40
C to +85
C, unless otherwise specified.
Symbol
V
CC
V
I
I
O
I
IK
T
stg
[1]
Parameter
supply voltage
input voltage
output current
input clamping current
storage temperature
Conditions
[2]
Min
0.5
0.5
-
50
65
Max
+7.0
+7.0
128
-
+150
Unit
V
V
mA
mA
C
V
O
< 0 V
V
I/O
= 0 V
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under
Section 8.
is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
[2]
8. Recommended operating conditions
Table 5.
Operating conditions
All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation.
Symbol
V
CC
V
IH
V
IL
T
amb
Parameter
supply voltage
HIGH-state input voltage
LOW-state input voltage
ambient temperature
operating in free air
Conditions
Min
4.5
2.0
-
40
Typ
-
-
-
-
Max
5.5
-
0.8
+85
Unit
V
V
V
C
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol
V
IK
I
I
I
CC
I
CC
V
pass
C
I
C
io(off)
Parameter
input clamping voltage
input leakage current
supply current
additional supply current
pass voltage
input capacitance
off-state input/output
capacitance
Conditions
V
CC
= 4.5 V; I
I
=
18
mA
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 5.5 V; I
O
= 0 mA;
V
I
= V
CC
or GND
per input pin; V
CC
= 5.5 V; one input
at 3.4 V, other inputs at V
CC
or GND
see
Figure 5
to
Figure 9
control pins; V
I
= 3 V or 0 V
port off; V
I
= 3 V or 0 V; OE = V
CC
[2]
T
amb
=
40 C
to +85
C
Min
-
-
-
-
-
-
-
Typ
[1]
-
-
-
-
-
2.5
4.0
Max
1.2
1
1.5
2.5
-
-
-
Unit
V
A
mA
mA
V
pF
pF
CBTD3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 21 November 2011
4 of 16
NXP Semiconductors
CBTD3861
10-bit level shifting bus switch with output enable
Table 6.
Static characteristics
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol
R
ON
Parameter
ON resistance
Conditions
V
CC
= 4.5 V; V
I
= 0 V; I
I
= 64 mA
V
CC
= 4.5 V; V
I
= 0 V; I
I
= 30 mA
V
CC
= 4.5 V; V
I
= 2.4 V; I
I
=
15
mA
[1]
[2]
[3]
All typical values are at V
CC
= 5 V, T
amb
= 25
C.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
Measured by the voltage drop between the nAn and the nBn terminals at the indicated current through the switch. ON resistance is
determined by the lowest voltage of the two (nAn or nBn) terminals.
[3]
[3]
[3]
T
amb
=
40 C
to +85
C
Min
-
-
-
Typ
[1]
5
5
17
Max
7
7
50
Unit
9.1 Typical pass voltage graphs
3.6
V
pass
(V)
3.2
(1)
001aak834
3.6
V
pass
(V)
(1)
001aak835
3.2
(2)
(2)
(3)
2.8
(4)
2.8
(3)
(4)
2.4
2.4
2.0
4.4
4.8
5.2
V
CC
(V)
5.6
2.0
4.4
4.8
5.2
V
CC
(V)
5.6
(1) I
SW
= 100
A
(2) I
SW
= 6 mA
(3) I
SW
=12 mA
(4) I
SW
= 24 mA
(1) I
SW
= 100
A
(2) I
SW
= 6 mA
(3) I
SW
=12 mA
(4) I
SW
= 24 mA
Fig 5.
Pass voltage versus supply voltage;
T
amb
= 85
C
(typical)
Fig 6.
Pass voltage versus supply voltage;
T
amb
= 70
C
(typical)
CBTD3861
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 21 November 2011
5 of 16
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