74LVC2G34
Dual buffer gate
Rev. 7 — 4 July 2012
Product data sheet
1. General description
The 74LVC2G34 provides two buffers.
Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of
these devices in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C.
NXP Semiconductors
74LVC2G34
Dual buffer gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC2G34GW
74LVC2G34GV
74LVC2G34GM
74LVC2G34GF
74LVC2G34GN
74LVC2G34GS
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SC-88
TSOP6
XSON6
XSON6
XSON6
XSON6
Description
plastic surface-mounted package; 6 leads
plastic surface-mounted package (TSOP6); 6 leads
Version
SOT363
SOT457
Type number
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
1.45
0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1
1
0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9
1.0
0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0
1.0
0.35 mm
SOT1115
SOT1202
4. Marking
Table 2.
Marking
Marking code
[1]
YA
Y34
YA
YA
YA
YA
Type number
74LVC2G34GW
74LVC2G34GV
74LVC2G34GM
74LVC2G34GF
74LVC2G34GN
74LVC2G34GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
1A
1Y
6
1
1
6
3
2A
2Y
4
3
1
4
mnb064
A
Y
001aac536
mnb063
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
74LVC2G34
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 4 July 2012
2 of 17
NXP Semiconductors
74LVC2G34
Dual buffer gate
6. Pinning information
6.1 Pinning
74LVC2G34
74LVC2G34
1A
GND
1
2
6
5
1Y
GND
V
CC
2A
2A
3
001aab676
1A
1
6
1Y
1A
GND
74LVC2G34
1
2
3
6
5
4
1Y
V
CC
2Y
2
5
V
CC
3
4
2Y
2A
4
2Y
001aab677
001aag030
Transparent top view
Transparent top view
Fig 4.
Pin configuration SOT363
and SOT457
Fig 5.
Pin configuration SOT886
Fig 6.
Pin configuration SOT891,
SOT1115 and SOT1202
6.2 Pin description
Table 3.
Symbol
1A
GND
2A
2Y
V
CC
1Y
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data output
7. Functional description
Table 4.
Input
nA
L
H
[1]
H = HIGH voltage level; L = LOW voltage level.
Function table
[1]
Output
nY
L
H
74LVC2G34
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 4 July 2012
3 of 17
NXP Semiconductors
74LVC2G34
Dual buffer gate
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[1][2]
[1][2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
250
+150
Unit
V
mA
V
mA
V
V
mA
mA
mA
mW
C
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
T
amb
=
40 C
to +125
C
[3]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For SC-88 and SC-74A packages: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
1.65
0
0
0
40
-
-
Typ
-
-
-
-
-
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
C
ns/V
ns/V
74LVC2G34
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 4 July 2012
4 of 17
NXP Semiconductors
74LVC2G34
Dual buffer gate
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
100 A;
V
CC
= 1.65 V to 5.5 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
24
mA; V
CC
= 3.0 V
I
O
=
32
mA; V
CC
= 4.5 V
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 100
A;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
I
OFF
input leakage
current
power-off
leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
V
CC
= 0 V; V
I
or V
O
= 5.5 V
40 C
to +85
C
Min
0.65V
CC
1.7
2.0
0.7V
CC
-
-
-
-
V
CC
0.1
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
Max
-
-
-
-
0.35V
CC
0.7
0.8
0.3V
CC
-
-
-
-
-
-
0.10
0.45
0.30
0.40
0.55
0.55
5
10
40 C
to +125
C
Min
0.65V
CC
1.7
2.0
0.7V
CC
-
-
-
-
V
CC
0.1
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.7
0.8
0.3V
CC
-
-
-
-
-
-
0.10
0.70
0.45
0.60
0.80
0.80
20
20
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
Unit
0.35V
CC
V
I
CC
I
CC
C
I
supply current V
I
= 5.5 V or GND; I
O
= 0 A;
V
CC
= 1.65 V to 5.5 V
additional
per pin; V
CC
= 2.3 V to 5.5 V;
supply current V
I
= V
CC
0.6 V; I
O
= 0 A
input
capacitance
V
CC
= 3.3 V; V
I
= GND to V
CC
-
-
-
0.1
5
2.5
10
500
-
-
-
-
40
5000
-
A
A
pF
[1]
All typical values are measured at V
CC
= 3.3 V and T
amb
= 25
C.
74LVC2G34
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 4 July 2012
5 of 17
嵌入式系统
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