74LVC841A
10-bit transparent latch with 5 V tolerant inputs/outputs;
3-state
Rev. 03 — 24 May 2004
Product data sheet
1. General description
The 74LVC841A is a high performance, low-power, low-voltage Si-gate CMOS device and
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can
handle 5 V. This feature allows the use of these devices as translators in a mixed
3.3 V and 5 V environment.
The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each
latch and 3-state outputs for bus-oriented applications. A latch enable (pin LE) input and
an output enable (pin OE) input are common to all internal latches. The 74LVC841A
consists of ten transparent latches with 3-state true outputs. When pin LE is HIGH, data at
the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes. When pin LE is LOW the
latches store the information that was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the ten latches
are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the pin OE input does not affect the state of the latches.
2. Features
s
s
s
s
s
s
s
s
5 V tolerant inputs/outputs; for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Flow-through pin-out architecture
Complies with JEDEC standard JESD8B/JESD36
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
Philips Semiconductors
74LVC841A
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns.
Symbol
Parameter
Conditions
C
L
= 50 pF;
V
CC
= 3.3 V
Min
-
-
-
-
-
V
CC
= 3.3 V
outputs enabled
outputs disabled
[1]
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
[2]
The condition is V
I
= GND to V
CC
.
[1] [2]
Typ
3.0
3.4
3.5
2.9
5.0
13
4
Max
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
pF
pF
pF
t
PHL
, t
PLH
propagation delay
Dn to Qn
propagation delay LE to Qn C
L
= 50 pF;
V
CC
= 3.3 V
t
PZH
, t
PZL
t
PHZ
, t
PLZ
C
I
C
PD
3-state output enable time
OE to Qn
3-state output disable time
OE to Qn
input capacitance
power dissipation
capacitance per latch
C
L
= 50 pF;
V
CC
= 3.3 V
C
L
= 50 pF;
V
CC
= 3.3 V
-
-
4. Ordering information
Table 2:
Ordering information
Package
Temperature
range
74LVC841AD
74LVC841ADB
74LVC841APW
74LVC841ABQ
Name
Description
plastic small outline package; 24 leads; body width
7.5 mm
plastic shrink small outline package; 24 leads; body
width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT137-1
SOT340-1
SOT355-1
Type number
−40 °C
to +125
°C
SO24
−40 °C
to +125
°C
SSOP24
−40 °C
to +125
°C
TSSOP24
−40 °C
to +125
°C
DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1
thin quad flat package; no leads; 24 terminals; body
3.5 x 5.5 x 0.85 mm
9397 750 13129
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 24 May 2004
2 of 21
Philips Semiconductors
74LVC841A
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
6. Pinning information
6.1 Pinning
terina 1
ine area
D0
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 LE
001aaa836
2
3
4
5
6
7
8
9
GND
1
GND 12
LE 13
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
D1
D2
D3
D4
D5
D6
D7
1
OE
841
841
D8 10
D9 11
D8 10
D9 11
GND 12
001aaa837
Transparent top view
(1) The die substrate is attached to this
pad using conductive die attach
material. It can not be used as a
supply pin or input.
Fig 5. Pin configuration for SO24 and
(T)SSOP24.
Fig 6. Pin configuration for DHVQFN24.
6.2 Pin description
Table 3:
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
9397 750 13129
Pin description
Symbol
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
LE
Q9
Q8
Description
output enable input (active LOW)
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
ground (0 V)
latch enable input (active LOW)
3-state latch output
3-state latch output
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 24 May 2004
5 of 21
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