74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Rev. 5 — 13 December 2011
Product data sheet
1. General description
The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type
inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all latches.
The 74HC373; 74HCT373 consists of eight D-type transparent latches with 3-state true
outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
D input changes.
When LE is LOW the latches store the information that was present at the D inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-
impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The 74HC373; 74HCT373 is functionally identical to:
•
74HC563; 74HCT563: but inverted outputs and different pin arrangement
•
74HC573; 74HCT573: but different pin arrangement
2. Features and benefits
3-state non-inverting outputs for bus oriented applications
Common 3-state output enable input
Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
3. Ordering information
Table 1.
Ordering information
Temperature range
74HC373N
74HCT373N
74HC373D
74HCT373D
74HC373DB
74HCT373DB
74HC373PW
74HCT373PW
74HC373BQ
74HCT373BQ
40 C
to +125
C
DHVQFN20
40 C
to +125
C
TSSOP20
40 C
to +125
C
SSOP20
40 C
to +125
C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
SOT163-1
SOT339-1
SOT360-1
SOT764-1
40 C
to +125
C
Name
DIP20
Description
plastic dual in-line package; 20 leads (300 mil)
Version
SOT146-1
Type number Package
4. Functional diagram
3
4
7
8
13
14
17
18
11
1
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
LATCH
1 TO 8
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
001aae050
Fig 1.
Functional diagram
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
2 of 26
NXP Semiconductors
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
OE
LE
11
3
4
7
8
13
14
17
18
LE
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
001aae048
1
11
EN
C1
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
1D
2
5
6
9
12
15
16
19
001aae049
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
LE
LE
LE
D
Q
LE
001aae051
Fig 4.
Logic diagram (one latch)
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LE LE
LATCH
2
LE LE
LATCH
3
LE LE
LATCH
4
LE LE
LATCH
5
LE LE
LATCH
6
LE LE
LATCH
7
LE LE
LATCH
8
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae052
Fig 5.
Logic diagram
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
3 of 26
NXP Semiconductors
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
74HC373
74HCT373
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
Q0
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
001aae046
74HC373
74HCT373
terminal 1
index area
2
3
4
5
6
7
8
9
GND 10
LE 11
GND
(1)
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
OE
1
D0
D1
Q1
Q2
D2
D3
Q3
GND 10
001aae047
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input.
Fig 6.
Pin configuration DIP20, SO20, SSOP20 and
TSSOP20
Fig 7.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
D0, D1, D2, D3, D4, D5, D6, D7
GND
LE
V
CC
Pin description
Pin
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
Description
3-state output enable input (active LOW)
3-state latch output
data input
ground (0 V)
latch enable input (active HIGH)
supply voltage
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
4 of 26
NXP Semiconductors
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
6. Functional description
6.1 Function table
Table 3.
Function table
[1]
Control
OE
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable
outputs
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
Operating mode
Input
LE
H
L
X
Dn
L
H
l
h
X
Internal latches
L
H
L
H
X
Output
Qn
L
H
L
H
Z
L
L
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP20 package
SO20 package
SSOP20 package
TSSOP20 package
DHVQFN20 package
[1]
[2]
[3]
[4]
For DIP20 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO20: P
tot
derates linearly with 8 mW/K above 70
C.
For SSOP20 and TSSOP20 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN20 package: P
tot
derates linearly with 4.5 mW/K above 60
C.
[1]
[2]
[3]
[3]
[4]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
-
65
-
-
Max
+7
20
20
35
+70
70
+150
750
500
500
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
mW
mW
mW
-
500
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
5 of 26
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