Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
FEATURES
•
Wide supply voltage range from 1.65 to 3.6 V
•
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
•
3.6 V tolerant inputs/outputs
•
CMOS low power consumption
•
Direct interface with TTL levels (2.7 to 3.6 V)
•
Power-down mode
•
Latch-up performance exceeds 250 mA
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay nCP to nQ, nQ
CONDITIONS
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
t
PHL
/t
PLH
propagation delay nSD, nRD to nQ, nQ
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
maximum clock frequency
input capacitance
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes 1 and 2
DESCRIPTION
74ALVC74
The 74ALVC74 is a dual positive-edge triggered, D-type
flip-flop with individual data (D), clock (CP), set (SD) and
reset (RD) inputs and complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
TYPICAL
3.7
2.6
2.8
2.7
3.5
2.5
3.1
2.3
425
3.5
35
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
MHz
pF
pF
2003 May 26
2
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYMBOL
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
V
CC
DESCRIPTION
asynchronous reset-direct input
(active LOW)
data input
clock input (LOW-to-HIGH,
edge-triggered)
asynchronous set-direct input
(active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
complement flip-flop output
true flip-flop output
asynchronous set-direct input
(active LOW)
clock input (LOW-to-HIGH,
edge-triggered)
data input
asynchronous reset-direct input
(active LOW)
supply voltage
GND
7
MNA417
74ALVC74
handbook, halfpage
1RD
1D
1CP
1SD
1Q
1Q
1
2
3
4
5
6
14 VCC
13 2RD
12 2D
74
11 2CP
10 2SD
9
2Q
8 2Q
Fig.1 Pin configuration SO14 and TSSOP14.
handbook, halfpage
1RD
1
VCC
14
13
12
2RD
2D
2CP
2SD
2Q
2
12
3
11
handbook, halfpage
1D
1CP
1SD
1Q
1Q
2
3
4
5
6
7
Top view
GND
8
2Q
4 10
1SD 2SD
SD
1Q
1D
Q
D
2D
2Q
1CP
CP
2CP
FF
1Q
Q
2Q
RD
1RD 2RD
1 13
5
9
GND
(1)
11
10
9
6
8
MDB105
MNA418
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.2 Pin configuration DHVQFN14.
Fig.3 Logic symbol.
2003 May 26
4
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