Philips Semiconductors
Product data
7-bit to 28-bit address register/driver with 3-state
outputs
FEATURES
PIN CONFIGURATION
74ALVCH16832
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
•
Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
4Y1
3Y1
GND
2Y1
1Y1
V
CC
A1
GND
A2
1
2
3
4
5
6
7
8
9
64 1Y2
63 2Y2
62 GND
61 3Y2
60 4Y2
59 V
CC
58 1Y3
57 2Y3
56 GND
55 3Y3
54 4Y3
53 GND
52 V
CC
51 GND
50 1Y4
49 2Y4
48 3Y4
47 4Y4
46 GND
45 1Y5
44 2Y5
43 V
CC
42 3Y5
41 4Y5
40 GND
39 GND
38 V
CC
37 1Y6
36 2Y6
135 GND
34 3Y6
33 4Y6
•
Bus hold on data inputs eliminates the need for external
pullup/pulldown resistors
DESCRIPTION
This 7 channel 1-bit to 4-bit address register/driver is designed for
2.3 V to 3.6 V V
CC
operation. This device is ideal for use in
applications in which a single address bus is driving four separate
memory locations. The 74ALVCH16832 can be used as a buffer or
a register, depending on the logic level of the select (SEL) input.
When SEL is a logic high, the device is in the buffer mode. The
outputs follow the inputs and are controlled by the two output-enable
(OE) inputs. Each OE controls two groups of seven outputs.
When SEL is a logic low, the device is in the register mode. The
register is an edge-triggered D-type flip-flop. On the positive
transition of the clock (CLK) input, data at the A inputs is stored in
the internal registers. OE operates the same as in the buffer mode.
When OE is a logic low, the outputs are in a normal logic state, (high
or low logic level). When OE is a logic high, the outputs are in the
high-impedance state.
Neither SEL of OE affect the internal operation of the flip-flops. Old
data can be retained or new data can be entered while the outputs
are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active buss-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
The 74ALVCH16832 is characterized for operation from –40 to
+85° C.
GND 10
A3 11
V
CC
12
NC 13
GND 14
CLK 15
OE1 16
OE2 17
SEL 18
GND 19
A4 20
A5 21
V
CC
22
GND 23
A6 24
GND 25
A7 26
V
CC
27
4Y7 28
3Y7 29
PIN DESCRIPTION
PIN(S)
1, 2, 4, 5, 28. 29, 31, 32, 33, 34,
36, 37, 41, 42, 44, 45, 47, 48, 49,
50, 54, 55, 57, 58, 60, 61, 63, 64
3, 8, 10, 14, 19, 23, 25, 30, 35,
39, 40, 46, 51, 53, 56, 62
6, 12, 22, 27, 38, 43, 52, 59
7, 9, 11, 20, 21, 24, 26
16, 17
15
18
SYMBOL
1Yn, 2Yn,
3Yn, 4Yn
GND
V
CC
An
OE1, OE2
CLK
SEL
FUNCTION
Outputs
GND 30
2Y7 31
1Y7 32
SV01912
Ground
Supply voltage
Inputs
Output enable
Clock
Select
ORDERING INFORMATION
PACKAGES
64-pin Plastic TSSOP
TEMPERATURE RANGE
–40 to +85
°C
ORDER CODE
74ALVCH16832DGG
DWG NUMBER
SOT646-1
2001 Dec 14
2
853-2311 27460
Philips Semiconductors
Product data
7-bit to 28-bit address register/driver with
3-state outputs
74ALVCH16832
LOGIC DIAGRAM (POSITIVE LOGIC)
16
5 1Y1
OE1
17
4
CLK
15
7
CLK
2 3Y1
A1
D
Q
1
4Y1
2Y1
OE2
SEL
18
to 6 other channels
SV01913
FUNCTION TABLE
Inputs
OE
H
L
L
L
L
SEL
X
H
H
L
L
CLK
X
X
X
↑
↑
A
X
L
H
L
H
Output
Y
Z
L
H
L
H
ABSOLUTE MAXIMUM RATINGS
Over recommended operating free-air temperature range (unless otherwise noted).
1
SYMBOL
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
, I
GND
Θ
JA
T
stg
PARAMETER
Supply voltage range
Input voltage range
Output voltage range
Input clamp current
Output clamp current
Continuous output current
Continuous current through each V
CC
or GND
Package thermal impedance
Storage temperature range
See Note 4
See Note 2
See Notes 2 and 3
V
I
< 0
V
O
< 0
CONDITIONS
RATING
–0.5 to +4.6
–0.5 to +4.6
–0.5 to V
CC
+0.5
–50
–50
"50
"100
106
–65 to +150
UNIT
V
V
V
mA
mA
mA
mA
°C/W
°C
NOTES:
1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. This value is limited to 4.6 V maximum.
4. The package thermal impedance is calculated in accordance with JESD 51.
2001 Dec 14
3
stm32/stm8
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