TSS901E
Intelligent and Flexible IEEE 1355 communication
controller for space
Description and Applications
The TSS901E provides an interface between a Data-
Strobe link - according to the IEEE Std 1355-1995
specification carrying a simple interprocessor
communication protocol - and a data processing node
consisting of a CPU and a communication and data
memory.
The TSS901E offers hardware supported execution of
the major parts of the interprocessor communication
protocol: data transfer between two nodes of a multi-
processor system is performed with minimal host CPU
intervention. The TSS901E can execute simple
commands to provide basic features for system control
functions; a provision of fault tolerant features exists as
well.
Although the TSS901E initial exploitation is for use in
multi-processor systems where the high speed links
standardisation is an important issue and where reliability
is a requirement, it could be used in applications such
as heterogeneous systems or modules without any
communication feature like special image compression
chips, some signal processors, application specific
programmable logic or mass memory.
The TSS901E may also be used in single board systems
where standardised high speed interfaces are needed and
systems containing "non-intelligent" modules such as A/
D-converter or sensor interfaces which can be assembled
with the TSS901E thanks to the "control by link" feature.
Features
q
3 identical bidirectional link channels allowing full
duplex communication under selectable transmit rate
from 1.25 up to 200 Mbit/s in each direction
a COmmunication Memory Interface (COMI)
provides autonomous accesses to a communication
memory which are controlled by an arbitration unit,
allowing two TSS901E to share one Dual Port Ram
without external arbitration
the scalable databus width (8/16/32 bit) allows
flexible integration with any CPU type
little or big endian mode is configurable
a HOst Control Interface (HOCI) gives read/write
accesses to the TSS901E configuration registers and
to the DS-link channels for the controlling CPU
q
device control via one of the three links allows its
use in systems without a local controller
link disconnect detection and parity check at token
(data and control) level; possible checksum
generation for packet level check
power saving mode relying on automatic transmit
rate reduction
a user’s manual of the TSS901E (also called
SMCS332) is available at:
http://www.omimo.be/companies/dasa_000.htm
q
q
q
q
q
q
q
The information contained herein is subject to change without notice.
No responsibility is assumed by Atmel Wireless & Microcontrollers
for using this publication and/or circuits described herein : nor for
any possible infringements of patents or other rights of third parties
which may result from its use.
Rev. B - July 29, 1999
1
TSS901E
1. Introduction
The TSS901E provides an interface between a Data-Strobe link according to the IEEE Std 1355-1995 specification
carrying the simple interprocessor communication protocol
1
and a data processing node consisting of a CPU and
communication and data memory. The TSS901E provides HW supported execution of the major parts of the simple
interprocessor communication protocol, particularly:
q
q
q
transfer of data between two modes of a multi-processor system with minimal host CPU intervention,
execution of simple commands to provide basic features for system control functions,
provision of fault tolerant features.
However, with disabling of features such as the protocol handling or with reduction of the transmit rate (TSS901E
automatically reduces transmit rate for sending null tokens) also low power usage is supported.
Receive
COMI
RX1_DS
TX1_DS
DS
macro
cell
CADR
CCTRL
CDATA
Protocol
HADR
HCTRL
Transmit
HOCI
Channel 1
HINT
HDATA
RX2_DS
TX2_DS
Channel 2
PRCI
RCPU
SES
UTIL
RX3_DS
TX3_DS
Test
Figure 1. TSS901E Block Diagram
Channel 3
JTAG
Target applications are heterogeneous multi-processor systems supported by scalable interfaces including the little/
big endian swapping. The TSS901E connects modules with different processors (e.g. 21020F, ERC32, TSC695E
and others). Any kind of network topology could be realized through the high speed point-to-point IEEE1355-links
(see chapter Applications).
1. Rastetter P. et.al., Simple Interprocessor Communication Protocol Specification, DIPSAPII-DAS-31-01, Issue 3, 08.10.96, also available on
the same web site as the users guide.
2
Rev. B - July 29, 1999
TSS901E
1.1 Interfaces
The TSS901E consists of the following blocks (See TSS901E block diagram):
q
bidirectional link channels,
all comprising the DS-link macro cell (DSM), receive and transmit sections (each
including FIFOs) and a protocol processing unit (PPU). Each channel allows full duplex communication up to
200 Mbit/s in each direction. With protocol command execution a higher level of communication is supported.
Link disconnect detection and parity check at token level are performed. A checksum generation for a check
at packet level can be enabled.
The transmit rate is selectable between 1.25 and 200 Mbit/s; an additional power saving mode can be enabled,
where the transmit rate is automatically reduced to 10 Mbit/s when only Null tokens are being transmitted over
the link. The default transmit rate is 10 Mbit/s. For special applications the data transmit rate can be programmed
to values even below 10 Mbit/s; the lowest possible (to be within the IEEE-1355 specification) transmit rate
is 1.25 Mbit/s (the next values are 2.5 and 5 Mbit/s).
q
Communication Memory Interface (COMI)
performs autonomous accesses to the communication memory
of the module to store data received via the links or to read data to be transmitted via the links. The COMI
consists of individual memory address generators for the receive and transmit direction of every DS link channel.
The access to the memory is controlled via an arbitration unit providing a fair arbitration scheme. Two TSS901E
can share one DPRAM without external arbitration.
The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type.
Operation in little or big endian mode is configurable through internal registers.
The COMI address bus is 16 bit wide allowing direct access of up to 64K words of the DPRAM. Two chip
select signals are provided to allow splitting of the 64k address space in two memory banks.
q
Host Control Interface (HOCI)
gives read and write access to the TSS901E configuration registers and to
the DS-link channels for the controlling CPU. Viewed from the CPU, the interface behaves like a peripheral
that generates acknowledges to synchronize the data transfers and which is located somewhere in the CPU's
address space.
Packets can be transmitted or received directly via the HOCI. In this case the Communication Memory (DPRAM)
is not strictly needed. However, in this case the packet size should be limited to avoid frequent CPU interaction.
The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type. The byte alignment
can be configured for little or big endian mode through an external pin.
Additionally the HOCI contains the interrupt signalling capability of the TSS901E by providing an interrupt
output, the interrupt status register and interrupt mask register to the local CPU.
A special pin is provided to select between control of the TSS901E by HOCI or by link. If control by link is
enabled, the host data bus functions as a 32-bit general purpose interface (GPIO).
q
Protocol Command Interface (PRCI)
that collects the decoded commands from all PPUs and forwards them
to external circuitry via 5 special pins.
JTAG Test Interface
that represents the boundary scan testing provisions specified by IEEE Standard 1149.1
of the Joint Testing Action Group (JTAG). The TSS901E' test access port and on-chip circuitry is fully compliant
with the IEEE 1149.1 specification. The test access port enables boundary scan testing of circuitry connected
to the TSS901E I/O pins.
q
3
Rev. B - July 29, 1999
TSS901E
1.2 Operation Modes
According to the different protocol formats expected for the operation of the TSS901E, two major operation modes
are implemented into the TSS901E. The operation modes are chosen individually for each link channel by setting
the respective configuration registers via the HOCI or via the link.
q
Transparent Mode (default after reset):
This mode allows complete transparent data transfer between two
nodes without performing any interpretation of the databytes and without generating any acknowledges. It is
completely up to the host CPU to interpret the received data and to generate acknowledges if required.
The TSS901E accepts EOP1 and EOP2 control tokens as packet delimiters and generates autonomously EOP1/
EOP2 (as configured) markers after each end of a transmission packet.
This mode also includes as a special submode:
•
Wormhole routing:
This mode allows hardware routing of packets by the TSS901E.
q
Simple Interprocessor Communication
(SIC)
Protocol Mode:
This mode executes the simple interprocessor
communication protocol as described in the protocol specification
1
. The following capabilities of the protocol
are implemented into the TSS901E:
•
interpretation of the first 4 data tokens as the header bytes of the protocol
•
autonomous execution of the simple control commands as described in the protocol specification
1
•
autonomous acknowledgement of received packets if configured
In transmit direction no interpretation of the data is performed. This means that for transmit packets, the four
header bytes must be generated by the host CPU and must be available as the first data read from the
communication memory. EOP1/EOP2 control tokens are automatically inserted by the TSS901E when one
configured transfer from the communication memory has finished.
1.3 TSS901E Control by Link
A feature of the TSS901E is the possibility to control the TSS901E not only via HOCI but via one of the three
links. This allows to use the TSS901E in systems without a local controller ( Controller, FPGA etc.). Since the
HOCI is no longer used in this operation mode, it is instead available as a set of general purpose I/O (GPIO) lines.
1.4 Wormhole Routing
The TSS901E introduces a wormhole routing function similar to the routing implemented in the ST-Microelectronics
C104 routing switch. Each of the three links and the TSS901E itself can be assigned an eight bit address. When
routing is enabled in the TSS901E, the first byte of a packet will be interpreted as the address destination byte,
analysed and removed from the packet (header deletion). If this address matches one of the two other link addresses
or the TSS901E address assigned previously, the packet will be automatically forwarded to this link or the FIFO
of the TSS901E. If the header byte does not match a link address, the packet will be written to the internal FIFO
as well and an error interrupt (maskable) will be raised.
1. Rastetter P. et.al., Simple Interprocessor Communication Protocol Specification, DIPSAPII-DAS-31-01, Issue 3, 08.10.96, also available on
the same web site as the users guide.
Rev. B - July 29, 1999
4
TSS901E
1.5 PPU Functional Description
Since the Protocol Processing Unit (PPU) determines a major part of the TSS901E functionality, the principal
blocks of the PPU and their function are described here. This functionality is provided for every DS link channel
of the TSS901E.
q
Protocol Execution Unit:
This unit serves as the main controller of the PPU block. It receives the tokens from
the DS macrocell and interprets (in protocol mode) the four header data characters received after an EOP1/
EOP2 control character. If the address field matches the link channel address and the command field contains
a valid command then forwarding of data into the receive FIFO is enabled. If the command field contains a
"simple control command" then the execution request is forwarded to the command execution unit.
The protocol execution unit also enables forwarding of header data characters to the acknowledge generator
and provides an error signal in case of address mismatch, wrong commands or disabled safety critical "simple
control commands".
The protocol execution unit is disabled in "transparent" or “wormhole routing” operation mode.
q
Receive, Transmit, Acknowledge:
The transmit and receive FIFOs decouple the DS link related operations
from the TSS901E related operations in all modes and such allows to keep the speed of the different units
even when the source or sink of data is temporarily blocked.
In the protocol mode a further FIFO (acknowledge FIFO) is used to decouple sending of acknowledges from
receiving new data when the transmit path is currently occupied by a running packet transmission.
q
Command Execution Unit:
This unit performs activating resp. deactivating of the CPU reset and the specific
external signals and provides the capability to reset one or all links inside the TSS901E, all actions requested
by the decoded commands from the protocol execution unit.
The unit contains a register controlling the enable/disable state of safety critical commands which is set into
the 'enable' state upon command request and which is reset after a safety critical command has been executed.
The CPU reset and the specific external signals are forwarded to the Protocol Command Interface (PRCI).
1.6 Fault Tolerance
The IEEE Std 1355-1995 specifies low level checks as link disconnect detection and parity check at token level.
The TSS901E provides, through the Protocol Processing Unit, features to reset a link or all links inside the TSS901E,
to reset the local CPU or to send special signals to the CPU commanded via the links.
Additionally it is possible to enable a checksum coder/decoder to have fault detection capabilities at packet level.
5
Rev. B - July 29, 1999
Microchip MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
