74HC137
3-to-8 line decoder, demultiplexer with address latches;
inverting
Rev. 03 — 11 November 2004
Product data sheet
1. General description
The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power
Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC
standard no. 7A.
The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address
inputs (An). The 74HC137 essentially combines the 3-to-8 decoder function with a 3-bit
storage latch. When the latch is enabled (LE = LOW), the 74HC137 acts as a 3-to-8 active
LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present
at the inputs before this transition, is stored in the latches. Further address changes are
ignored as long as LE remains HIGH.
The output enable input (E1 and E2) controls the state of the outputs independent of the
address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.
The 74HC137 is ideally suited for implementing non-overlapping decoders in 3-state
systems and strobed (stored address) applications in bus oriented systems.
2. Features
s
s
s
s
s
s
Combines 3-to-8 decoder with 3-bit latch
Multiple input enable for easy expansion or independent controls
Active LOW mutually exclusive outputs
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Multiple package options
s
Specified from
−40 °C
to +80
°C
and from
−40 °C
to +125
°C.
Philips Semiconductors
74HC137
3-to-8 line decoder, demultiplexer with address latches; inverting
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Symbol
t
PHL
, t
PLH
Parameter
propagation delay
An to Yn
LE to Yn
E1 to Yn
E2 to Yn
C
I
C
PD
[1]
Conditions
C
L
= 15 pF; V
CC
= 5 V
Min
-
-
-
-
-
Typ
18
17
15
15
3.5
57
Max
-
-
-
-
-
-
Unit
ns
ns
ns
ns
pF
pF
input capacitance
power dissipation
capacitance
V
I
= GND to V
CC
[1]
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
4. Ordering information
Table 2:
Ordering information
Package
Temperature range
74HC137N
74HC137D
74HC137DB
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP16
SO16
SSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
Version
SOT38-4
SOT109-1
SOT338-1
Type number
9397 750 13804
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 November 2004
2 of 19
Philips Semiconductors
74HC137
3-to-8 line decoder, demultiplexer with address latches; inverting
5. Functional diagram
4
LE
Y0 15
Y1 14
1 A0
2 A1
3 A2
INPUT
LATCHES
3 TO 8
DECODER
Y2 13
Y3 12
Y4 11
Y5 10
Y6 9
Y7 7
5 E1
6 E2
001aab881
Fig 1. Functional diagram
DX
4
1
2
4
LE
Y0
Y1
1
2
3
A0
INPUT
A1
LATCHES
A2
Y2
Y3
3 TO 8
DECODER Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
4
1
2
3
E1
5
6
E2
001aab879
C8
0
8D,G
2
0
7
0
1
2
3
4
5
15
14
13
12
11
10
9
7
3
5
6
&
6
7
X/Y
C8
8D,1
8D,2
8D,4
0
1
2
3
4
5
5
6
EN
001aab880
15
14
13
12
11
10
9
7
&
6
7
Fig 2. Logic symbol
Fig 3. IEC logic symbol
9397 750 13804
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 November 2004
3 of 19
Philips Semiconductors
74HC137
3-to-8 line decoder, demultiplexer with address latches; inverting
A0
A0
LE
LATCH
A0
LE
Y0
Y1
A1
A1
LE
LATCH
A1
LE
Y2
A2
A2
LE
LATCH
A2
LE
Y3
Y4
LE
Y5
Y6
Y7
E1
001aab882
E2
Fig 4. Logic diagram
6. Pinning information
6.1 Pinning
A0
A1
A2
LE
E1
E2
Y7
GND
1
2
3
4
16 V
CC
15 Y0
14 Y1
13 Y2
137
5
6
7
8
001aab878
12 Y3
11 Y4
10 Y5
9
Y6
Fig 5. Pin configuration
9397 750 13804
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 November 2004
4 of 19
Philips Semiconductors
74HC137
3-to-8 line decoder, demultiplexer with address latches; inverting
6.2 Pin description
Table 3:
Symbol
A0
A1
A2
LE
E1
E2
Y7
GND
Y6
Y5
Y4
Y3
Y2
Y1
Y0
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
data input 0
data input 1
data input 2
latch enable input (active LOW)
data enable input 1 (active LOW)
data enable input 2 (active HIGH)
multiplexer output 7
ground (0 V)
multiplexer output 6
multiplexer output 5
multiplexer output 4
multiplexer output 3
multiplexer output 2
multiplexer output 1
multiplexer output 0
positive supply voltage
7. Functional description
7.1 Function table
Table 4:
Enable
LE
H
X
X
L
E1
L
H
X
L
E2
H
X
L
H
Function table
[1]
Input
A0
X
X
X
L
H
L
H
L
H
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
Output
A1
X
X
X
L
L
H
H
L
L
H
H
A2
X
X
X
L
L
L
L
H
H
H
H
Y0
stable
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
Y1
Y2
Y3
Y4
Y5
Y6
Y7
9397 750 13804
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 November 2004
5 of 19
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