Freescale Semiconductor
Technical Data
DATA SHEET
MC100ES6139
Rev 3, 06/2005
3.3 V ECL/PECL/HSTL/LVDS ÷2/4,
3.3 V ECL/PECL/HSTL/LVDS
÷2/4,
÷4/5/6 Clock Generation Chip
MC100ES6139
÷4/5/6
Clock Generation Chip
MC100ES6139
The MC100ES6139 is a low skew
÷2/4, ÷4/5/6
clock generation chip designed
explicitly for low skew clock generation applications. The internal dividers are
synchronous to each other, therefore, the common output edges are all precisely
aligned. The device can be driven by either a differential or single-ended ECL or,
if positive power supplies are used, LVPECL input signals. In addition, by using
the V
BB
output, a sinusoidal source can be AC coupled into the device. If a single-
ended input is to be used, the V
BB
output should be connected to the CLK input
and bypassed to ground via a 0.01
µF
capacitor.
The common enable (EN) is synchronous so that the internal dividers will only
be enabled/disabled when the internal clock is already in the LOW state. This
avoids any chance of generating a runt clock pulse on the internal clock when the
device is enabled/disabled as can happen with an asynchronous control. The
internal enable flip-flop is clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the negative edge of the clock
input.
Upon startup, the internal flip-flops will attain a random state; therefore, for
systems which utilize multiple ES6139s, the master reset (MR) input must be
asserted to ensure synchronization. For systems which only use one ES6139,
the MR pin need not be exercised as the internal divider design ensures
synchronization between the
÷2/4
and the
÷4/5/6
outputs of a single device. All
V
CC
and V
EE
pins must be externally connected to power supply to guarantee
proper operation.
The 100ES Series contains temperature compensation.
Features
•
•
•
•
•
•
•
•
•
•
Maximum Frequency >1.0 GHz Typical
50 ps Output-to-Output Skew
PECL Mode Operating Range: V
CC
= 3.135 V to 3.8 V with V
EE
= 0 V
ECL Mode Operating Range: V
CC
= 0 V with V
EE
= –3.135 V to –3.8 V
Open Input Default State
Synchronous Enable/Disable
Master Reset for Synchronization of Multiple Chips
V
BB
Output
LVDS and HSTL Input Compatible
20-Lead Pb-Free Package Available
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
ORDERING INFORMATION
Device
MC100ES6139DT
MC100ES6139DTR2
MC100ES6139EJ
MC100ES6139EJR2
Package
TSSOP-20
TSSOP-20
TSSOP-20 (Pb-Free)
TSSOP-20 (Pb-Free)
IDT™
3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip
MC100ES6139
© Freescale Semiconductor, Inc., 2005. All
acquired by Integrated Device Technology, Inc
Freescale Timing Solutions Organization has been
rights reserved.
1
MC100ES6139
3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip
NETCOM
V
CC
20
Q0
19
Q0
18
Q1
17
Q1
16
Q2
15
Q2
14
Q3
13
Q3
12
V
EE
11
Table 1. Pin Description
Pin
CLK
(1)
, CLK
(1)
EN
(1)
MR
(1)
Function
ECL Diff Clock Inputs
ECL Sync Enable
ECL Master Reset
ECL Reference Output
ECL Diff
÷2/4
Outputs
ECL Diff
÷4/5/6
Outputs
ECL Freq. Select Input
÷2/4
ECL Freq. Select Input
÷4/5/6
ECL Freq. Select Input
÷4/5/6
ECL Positive Supply
ECL Negative Supply
1
V
CC
2
EN
3
DIVSELb0
4
CLK
5
CLK
6
V
BB
7
MR
8
V
CC
9
DIVSELb1
10
DIVSELa
V
BB
Q0, Q1, Q0, Q1
Q2, Q3, Q2, Q3
DIVSELa
(1)
DIVSELb0
(1)
DIVSELb1
(1)
Warning: All V
CC
and V
EE
pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout
(Top View)
V
CC
V
EE
1. Pins will default low when left open.
DIVSELa
CLK
CLK
Q0
÷2/4
R
Q0
Q1
Q1
Q2
÷4/5/6
R
MR
DIVSELb0
DIVSELb1
V
EE
Q2
Q3
Q3
EN
Figure 2. Logic Diagram
Table 2. Function Tables
CLK
Z
ZZ
X
X = Don’t Care
Z = Low-to-High Transition
ZZ = High-to-Low Transition
DIVSELa
L
H
DIVSELb0
L
H
L
H
DIVSELb1
L
L
H
H
Q0:1 Outputs
Divide by 2
Divide by 4
Q2:3 Outputs
Divide by 4
Divide by 6
Divide by 5
Divide by 5
EN
L
H
X
MR
L
L
H
Function
Divide
Hold Q0:3
Reset Q0:3
MC100ES6139
IDT™
3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip
MC100ES6139
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Advanced Clock Drivers Device Data
2
Freescale Semiconductor
2
MC100ES6139
3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip
NETCOM
CLK
Q (÷2)
Q (÷4)
Q (÷5)
Q (÷6)
Figure 3. Timing Diagram
CLK
t
RR
RESET
Q (÷n)
Figure 4. Timing Diagram
Table 3. Attributes
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Value
75 kΩ
75 kΩ
> 4 kV
> 200 V
> 2 kV
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
IDT™
3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip
MC100ES6139
MC100ES6139
3
Advanced Clock Drivers Device Data
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Freescale Semiconductor
3
MC100ES6139
3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip
NETCOM
Table 4. Maximum Ratings
(1)
Symbol
V
CC
V
EE
V
I
I
out
I
BB
TA
T
stg
θ
JA
Parameter
PECL Mode Power Supply
ECL Mode Power Supply
PECL Mode Input Voltage
ECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
≤
V
CC
V
I
≥
V
EE
Condition 2
Rating
3.9
–3.9
3.9
–3.9
50
100
± 0.5
–40 to +85
–65 to +150
74
64
Units
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
1. Maximum Ratings are those values beyond which device damage may occur.
Table 5. DC Characteristics
(V
CC
= 0 V, V
EE
= –3.8 V to –3.135 V or V
CC
= 3.135 V to 3.8 V, V
EE
= 0 V)
(1)
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage
(2)
Output LOW Voltage
(2)
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Reference Voltage
Differential Input Voltage
(3)
Differential Cross Point Voltage
(4)
Input HIGH Current
Input LOW Current
0.5
–40°C
Min
Typ
35
Max
60
Min
0°C to 85°C
Typ
35
Max
60
V
CC
–750
V
CC
–880
V
CC
–1475
V
CC
–1200
1.3
V
CC
–1.1
150
0.5
Unit
mA
mV
mV
mV
mV
mV
V
V
µA
µA
V
CC
–1150 V
CC
–1020 V
CC
–800 V
CC
–1200 V
CC
–970
V
CC
–1165
V
CC
–1810
V
CC
–1400
0.12
V
EE
+0.2
V
CC
–880 V
CC
–1165
V
CC
–1475 V
CC
–1810
V
CC
–1200 V
CC
–1400
1.3
V
CC
–1.1
150
0.12
V
EE
+0.2
V
CC
–1950 V
CC
–1620 V
CC
–1250 V
CC
–2000 V
CC
–1680 V
CC
–1300
1. MC100ES6139 circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
2. All loading with 50
Ω
to V
CC
–2.0 volts.
3. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
4. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
MC100ES6139
IDT™
3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip
MC100ES6139
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Advanced Clock Drivers Device Data
4
Freescale Semiconductor
4
MC100ES6139
3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip
NETCOM
Table 6. AC Characteristics
(V
CC
= 0 V, V
EE
= –3.8 V to –3.135 V or V
CC
= 3.135 V to 3.8 V, V
EE
= 0 V)
(1)
Symbol
f
max
t
PLH
,
t
PHL
t
RR
t
s
t
h
t
PW
t
SKEW
Characteristic
Maximum Frequency
Propagation Delay
Reset Recovery
Setup Time
Hold Time
EN, CLK
DIVSEL, CLK
CLK, EN
CLK, DIVSEL
MR
CLK, Q (Diff)
MR, Q
550
400
200
200
400
100
200
550
100
120
180
50
140
450
100
50
300
1
200
V
EE
+0.2
50
1200
200
–40°C
Min
Typ
>1
850
850
550
400
200
200
400
100
200
550
100
120
180
50
140
450
100
50
300
1
1200
200
Max
Min
25°C
Typ
>1
850
850
550
400
200
200
400
100
200
550
100
120
180
50
140
450
100
50
300
1
1200
V
CC
–1.2
300
Max
Min
85°C
Typ
>1
850
850
Max
Unit
GHz
ps
ps
ps
ps
ps
ps
Minimum Pulse Width
Within Device Skew
Q, Q
Q, Q @ Same Frequency
Device-to-Device Skew
(2)
(RSM 1σ)
t
JITTER
Cycle-to-Cycle Jitter
V
PP
V
CMR
t
r
t
f
ps
mV
V
ps
Input Voltage Swing (Differential)
Differential Cross Point Voltage
Output Rise/Fall Times
(20% – 80%)
Q, Q
V
CC
–1.2 V
EE
+0.2
300
50
V
CC
–1.2 V
EE
+0.2
300
50
1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50
Ω
to V
CC
–2.0 V.
2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are
measured from the cross point of the inputs to the cross point of the outputs.
Q
Driver
Device
Q
50
Ω
50
Ω
D
Receiver
Device
D
V
TT
V
TT
= V
CC
–- 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation
IDT™
3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/5/6 Clock Generation Chip
MC100ES6139
MC100ES6139
5
Advanced Clock Drivers Device Data
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Freescale Semiconductor
5
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