MM74HC423A Dual Retriggerable Monostable Multivibrator
September 1983
Revised January 2004
MM74HC423A
Dual Retriggerable Monostable Multivibrator
General Description
The 74HC423A high speed monostable multivibrators (one
shots) utilize advanced silicon-gate CMOS technology.
They feature speeds comparable to low power Schottky
TTL circuitry while retaining the low power and high noise
immunity characteristic of CMOS circuits.
Each multivibrator features both a negative, A, and a posi-
tive, B, transition triggered input, either of which can be
used as an inhibit input. Also included is a clear input that
when taken LOW resets the one shot. The MM74HC423A
cannot be triggered from clear.
The MM74HC423A is retriggerable. That is, it may be trig-
gered repeatedly while its outputs are generating a pulse
and the pulse will be extended.
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS techniques. The out-
put pulse equation is simply: PW
=
(R
EXT
) (C
EXT
); where
PW
is in seconds, R is in ohms, and C is in farads. All inputs
are protected from damage due to static discharge by
diodes to V
CC
and ground.
Features
s
Typical propagation delay: 40 ns
s
Wide power supply range: 2V–6V
s
Low quiescent current: 80
µ
A maximum (74HC Series)
s
Low input current: 1
µ
A maximum
s
Fanout of 10 LS-TTL loads
s
Simple pulse width formula T
=
RC
s
Wide pulse range: 400 ns to
∞
(typ)
s
Part to part variation:
±
5% (typ)
s
Schmitt Trigger A & B inputs allow rise and fall times to
be as slow as one second
Ordering Code:
Order Number
MM74HC423AM
(Note 1)
MM74HC423ASJ
MM74HC423AMTC
(Note 1)
MM74HC423AN
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Note 1:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Timing Component
Top View
© 2004 Fairchild Semiconductor Corporation
DS005338
Note:
Pin 6 and Pin 14 must be hard-wired to GND.
www.fairchildsemi.com
MM74HC423A
Truth Table
Inputs
Clear
L
X
X
H
H
H
L
↑
↓
HIGH Level
LOW Level
Transition from LOW-to-HIGH
Transition from HIGH-to-LOW
=
One HIGH Level Pulse
=
One LOW Level Pulse
X
=
Irrelevant
=
=
=
=
Outputs
B
X
X
L
Q
L
L
Q
H
H
A
X
H
X
L
↑
H
↓
L
H
Logic Diagram
www.fairchildsemi.com
2
MM74HC423A
Theory of Operation
FIGURE 1.
TRIGGER OPERATION
As shown in Figure 1 and the Logic Diagram before an
input trigger occurs, the one-shot is in the quiescent state
with the Q output LOW, and the timing capacitor C
EXT
com-
pletely charged to V
CC
. When the trigger input A goes from
V
CC
to GND (while inputs B and clear are held to V
CC
) a
valid trigger is recognized, which turns on comparator C1
and N-Channel transistor N11. At the same time the output
latch is set. With transistor N1 on, the capacitor C
EXT
rap-
idly discharges toward GND until V
REF1
is reached. At this
point the output of comparator C1 changes state and tran-
sistor N1 turns OFF. Comparator C1 then turns OFF while
at the same time comparator C2 turns on. With transistor
N1 OFF, the capacitor C
EXT
begins to charge through the
timing resistor, R
EXT
, toward V
CC
. When the voltage across
C
EXT
equals V
REF2
, comparator C2 changes state causing
the output latch to reset (Q goes LOW) while at the same
time disabling comparator C2. This ends the timing cycle
with the one-shot in the quiescent state, waiting for the next
trigger.
A valid trigger is also recognized when trigger input B goes
from GND to V
CC
(while input A is at GND and input clear
is at V
CC
2.)
It should be noted that in the quiescent state C
EXT
is fully
charged to V
CC
causing the current through resistor R
EXT
to be zero. Both comparators are “OFF” with the total
device current due only to reverse junction leakages. An
added feature of the MM74HC423A is that the output latch
is set via the input trigger without regard to the capacitor
voltage. Thus, propagation delay from trigger to Q is inde-
pendent of the value of C
EXT
, R
EXT
, or the duty cycle of the
input waveform.
RETRIGGER OPERATION
The MM74HC423A is retriggered if a valid trigger occurs 3
followed by another trigger 4 before the Q output has
returned to the quiescent (zero) state. Any retrigger, after
the timing node voltage at pin or has begun to rise from
V
REF1
, but has not yet reached V
REF2
, will cause an
increase in output pulse width T. When a valid retrigger is
initiated 4, the voltage at the R/C
EXT
pin will again drop to
V
REF1
before progressing along the RC charging curve
toward V
CC
. The Q output will remain high until time T, after
the last valid retrigger.
Because the trigger-control circuit flip-flop resets shortly
after C
X
has discharged to the reference voltage of the
lower reference circuit, the minimum retrigger time, t
rr
is a
function of internal propagation delays and the discharge
time of C
X
:
Another removal/retrigger time occurs when a short clear
pulse is used. Upon receipt of a clear, the one shot must
charge the capacitor up to the upper trip point before the
one shot is ready to receive the next trigger. This time is
dependent on the capacitor used and is approximately:
3
www.fairchildsemi.com
MM74HC423A
Theory of Operation
RESET OPERATION
(Continued)
clear input is held LOW, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will
not change. Since the Q output is reset when an input low
level is detected on the Clear input, the output pulse T can
be made significantly shorter than the minimum pulse width
specification.
These one shots may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on clear sets the reset latch and causes the capacitor to be
fast charged to V
CC
by turning on transistor Q1 5. When
the voltage on the capacitor reaches V
REF2
, the reset latch
will clear and then be ready to accept another pulse. If the
Typical Output Pulse Width vs.
Timing Components
Typical 1ms Pulse Width Variation vs. Supply
Typical Distribution of Output
Pulse Width, Part to Part
Minimum R
EXT
vs. Supply Voltage
Typical 1ms Pulse Width Variation vs. Temperature
Note:
R and C are not subjected to temperature. The C is polypropylene.
www.fairchildsemi.com
4
MM74HC423A
Absolute Maximum Ratings
(Note 2)
(Note 3)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current,
per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 4)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
°
C
600 mW
500 mW
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Maximum Input Rise and Fall Time
(Clear Input)
V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
1000
500
400
ns
ns
ns
2
0
Max
6
V
CC
Units
V
V
−
0.5V to
+
7.0V
−
1.5V to V
CC
+
1.5V
−
0.5V to V
CC
+
0.5V
±
20 mA
±
25 mA
±
50 mA
−
65
°
C to
+
150
°
C
−
40
+
85
°
C
Note 2:
Maximum Ratings are those values beyond which damage to the
device may occur.
Note 3:
Unless otherwise specified all voltages are referenced to ground.
Note 4:
Power Dissipation Temperature Derating: Plastic “N” Package:
−
12mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
Conditions
(Note 5)
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0
4.5
6.0
T
A
=
25°C
Typ
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.96
5.46
0
0
0
0.1
0.1
0.1
0.26
0.26
0.5
±0.1
8.0
36
0.33
0.7
80
1.0
2.0
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
5.0
±1.0
80
110
1.3
2.6
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
5.0
±1.0
160
130
1.6
3.2
µA
µA
µA
µA
mA
mA
V
V
V
V
Units
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
V
OL
Maximum LOW Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
2.0V
4.5V
6.0V
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4 mA
|I
OUT
|
≤
5.2 mA
I
IN
I
IN
I
CC
I
CC
Maximum Input Current
(Pins 7, 15)
Maximum Input Current
(all other pins)
Maximum Quiescent
Supply Current (standby)
Maximum Active Supply
Current (per
monostable)
V
IN
=
V
CC
or GND
I
OUT
=
0
µA
V
IN
=
V
CC
or GND
R/C
EXT
=
0.5V
CC
2.0V
4.5V
6.0V
6.0V
V
IN
=
V
CC
or GND
6.0V
V
IN
=
V
CC
or GND
4.5V
6.0V
5.0V
4.5V
6.0V
Note 5:
For a power supply of 5V
±10%
the worst-case output voltages (V
OH
, V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when design-
ing with this supply. Worst-case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst-case leakage current
(I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
5
www.fairchildsemi.com
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
