SPANSION
Data Sheet
TM
Flash Memory
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
TM
product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20888-7E
FLASH MEMORY
CMOS
8 M (1 M
×
8/512 K
×
16) BIT
MBM29LV800TE
60/70/90
/MBM29LV800BE
60/70/90
■
DESCRIPTION
The MBM29LV800TE/BE are a 8 M-bit, 3.0 V-only Flash memory organized as 1 M bytes of 8 bits each or
512 Kwords of 16 bits each. The MBM29LV800TE/BE are offered in a 48-pin TSOP (1) , 48-pin CSOP and 48-
ball FBGA package. These devices are designed to be programmed in a system with the standard system 3.0 V
V
CC
supply. 12.0 V V
PP
and 5.0 V V
CC
are not required for write or erase operations. The devices can also be
reprogrammed in standard EPROM programmers.
(Continued)
■
PRODUCT LINE UP
Part No.
Ordering Part No.
+0.3
V
V
CC
=
3.3 V
−0.3
V
+0.6
V
V
CC
=
3.0 V
−0.3
V
MBM29LV800TE/BE
60
⎯
60
60
30
⎯
70
70
70
30
⎯
90
90
90
35
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
■
PACKAGES
48-pin Plastic TSOP (1)
48-pin Plastic CSOP
48-ball Plastic FBGA
(FPT-48P-M19)
(LCC-48P-M03)
(BGA-48P-M20)
Retired Product DS05-20888-7E_July 31, 2007
MBM29LV800TE/BE
60/70/90
(Continued)
The standard MBM29LV800TE/BE offer access times 60 ns, 70 ns and 90 ns, allowing operation of high-speed
microprocessors without wait state. To eliminate bus contention, the devices have separate chip enable (CE) ,
write enable (WE) , and output enable (OE) controls.
The MBM29LV800TE/BE are pin and command set compatible with JEDEC standard E
2
PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV800TE/BE are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV800TE/BE are erased when shipped from the
factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally resets to the read mode.
The MBM29LV800TE/BE also have hardware RESET pins. When this pin is driven low, execution of any
Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then
reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset
occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically
reset to the read mode and will have erroneous data stored in the address locations being programmed or
erased. These locations need re-writing after the Reset. Resetting the device enables the system’s
microprocessor to read the boot-up firmware from the Flash memory.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29LV800TE/BE memory electrically erase all bits
within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word
at a time using the EPROM programming mechanism of hot electron injection.
Retired Product DS05-20888-7E_July 31, 2007
5
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