PUML1/DG
50 V, 200 mA NPN general-purpose transistor/
100 mA NPN resistor-equipped transistor
Rev. 01 — 14 July 2008
Product data sheet
1. Product profile
1.1 General description
NPN general-purpose transistor and NPN Resistor-Equipped Transistor (RET) in one
SOT363 (SC-88) very small Surface-Mounted Device (SMD) plastic package.
1.2 Features
I
General-purpose transistor:
N
200 mA collector current I
C
I
Resistor-equipped transistor:
N
Built-in bias resistors
I
Simplifies circuit design
I
Reduces component count
I
Reduces pick and place costs
I
Very small SMD plastic package
I
AEC-Q101 qualified
1.3 Applications
I
Inverter and switches
I
Low-frequency amplifier
I
Driver stages
1.4 Quick reference data
Table 1.
Quick reference data
Conditions
open base
V
CE
= 10 V;
I
C
= 2 mA
open base
Min
-
-
210
Typ
-
-
-
Max
50
200
340
Unit
V
mA
Symbol Parameter
TR1 (general-purpose transistor)
V
CEO
I
C
h
FE
collector-emitter voltage
collector current
DC current gain
TR2 (resistor-equipped transistor)
V
CEO
I
O
R1
R2/R1
collector-emitter voltage
output current
bias resistor 1 (input)
bias resistor ratio
-
-
7
0.8
-
-
10
1
50
100
13
1.2
V
mA
kΩ
NXP Semiconductors
PUML1/DG
50 V, 200 mA NPN general-purpose transistor/100 mA NPN RET
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
Pinning
Description
emitter TR1
base TR1
output (collector) TR2
GND (emitter) TR2
input (base) TR2
collector TR1
1
2
3
006aab253
Simplified outline
6
5
4
Graphic symbol
6
5
4
R1
R2
TR2
1
2
3
TR1
3. Ordering information
Table 3.
Ordering information
Package
Name
PUML1/DG
SC-88
Description
plastic surface-mounted package; 6 leads
Version
SOT363
Type number
4. Marking
Table 4.
Marking codes
Marking code
[1]
PA*
Type number
PUML1/DG
[1]
* = -: made in Hong Kong
* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CBO
V
CEO
V
EBO
I
C
I
CM
I
BM
Parameter
collector-base voltage
collector-emitter voltage
emitter-base voltage
collector current
peak collector current
peak base current
single pulse;
t
p
≤
1 ms
single pulse;
t
p
≤
1 ms
Conditions
open emitter
open base
open collector
Min
-
-
-
-
-
-
Max
60
50
6
200
200
100
Unit
V
V
V
mA
mA
mA
TR1 (general-purpose transistor)
PUML1_DG_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2008
2 of 12
NXP Semiconductors
PUML1/DG
50 V, 200 mA NPN general-purpose transistor/100 mA NPN RET
Table 5.
Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
P
tot
V
CBO
V
CEO
V
EBO
V
I
Parameter
total power dissipation
collector-base voltage
collector-emitter voltage
emitter-base voltage
input voltage
positive
negative
I
O
I
CM
P
tot
Per device
P
tot
T
j
T
amb
T
stg
[1]
Conditions
T
amb
≤
25
°C
open emitter
open base
open collector
[1]
Min
-
-
-
-
-
-
-
Max
200
50
50
10
+40
−10
100
100
200
300
150
+150
+150
Unit
mW
V
V
V
V
V
mA
mA
mW
mW
°C
°C
°C
TR2 (resistor-equipped transistor)
output current
peak collector current
total power dissipation
total power dissipation
junction temperature
ambient temperature
storage temperature
single pulse;
t
p
≤
1 ms
T
amb
≤
25
°C
T
amb
≤
25
°C
[1]
-
-
-
-
−55
−65
[1]
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
300
P
tot
(mW)
200
006aab254
100
0
−75
−25
25
75
125
175
T
amb
(°C)
FR4 PCB, standard footprint
Fig 1.
Per transistor: Power derating curve
PUML1_DG_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2008
3 of 12
NXP Semiconductors
PUML1/DG
50 V, 200 mA NPN general-purpose transistor/100 mA NPN RET
6. Thermal characteristics
Table 6.
Symbol
R
th(j-a)
Per device
R
th(j-a)
[1]
Thermal characteristics
Parameter
Conditions
[1]
Min
-
Typ
-
Max
625
Unit
K/W
Per transistor
thermal resistance from junction in free air
to ambient
thermal resistance from junction in free air
to ambient
[1]
-
-
417
K/W
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
10
3
Z
th(j-a)
(K/W)
10
2
006aab255
duty cycle =
1
0.75
0.5
0.33
0.2
0.1
0.05
0.02
10
0.01
0
1
10
−5
10
−4
10
−3
10
−2
10
−1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, standard footprint
Fig 2.
Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration
PUML1_DG_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2008
4 of 12
NXP Semiconductors
PUML1/DG
50 V, 200 mA NPN general-purpose transistor/100 mA NPN RET
7. Characteristics
Table 7.
Characteristics
T
amb
= 25
°
C unless otherwise specified.
Symbol Parameter
TR1 (general-purpose transistor)
I
CBO
collector-base cut-off
current
emitter-base cut-off
current
DC current gain
collector-emitter
saturation voltage
transition frequency
V
CB
= 60 V; I
E
= 0 A
V
CB
= 60 V; I
E
= 0 A;
T
j
= 150
°C
V
EB
= 5 V; I
C
= 0 A
V
CE
= 2 V; I
C
= 100 mA
V
CE
= 10 V; I
C
= 2 mA
V
CEsat
f
T
I
C
= 100 mA; I
B
= 10 mA
V
CE
= 10 V; I
C
= 2 mA;
f = 100 MHz
V
CE
= 6 V; I
C
= 10 mA;
f = 100 MHz
C
c
collector capacitance
V
CB
= 10 V; I
E
= i
e
= 0 A;
f = 1 MHz
V
CB
= 50 V; I
E
= 0 A
V
CE
= 30 V; I
B
= 0 A
V
CE
= 30 V; I
B
= 0 A;
T
j
= 150
°C
V
EB
= 5 V; I
C
= 0 A
V
CE
= 5 V; I
C
= 5 mA
I
C
= 10 mA; I
B
= 0.5 mA
V
CE
= 5 V; I
C
= 100
µA
V
CE
= 0.3 V; I
C
= 10 mA
-
-
-
90
210
-
100
-
-
-
-
-
-
-
-
-
230
-
10
5
10
-
340
250
-
-
3
mV
MHz
MHz
pF
nA
µA
nA
Conditions
Min
Typ
Max
Unit
I
EBO
h
FE
TR2 (resistor-equipped transistor)
I
CBO
I
CEO
collector-base cut-off
current
collector-emitter cut-off
current
emitter-base cut-off
current
DC current gain
collector-emitter
saturation voltage
off-state input voltage
on-state input voltage
bias resistor 1 (input)
bias resistor ratio
collector capacitance
V
CB
= 10 V; I
E
= i
e
= 0 A;
f = 1 MHz
-
-
-
-
30
-
-
2.5
7
0.8
-
-
-
-
-
-
-
1.1
1.8
10
1
-
100
1
50
400
-
150
0.8
-
13
1.2
2.5
pF
mV
V
V
kΩ
nA
µA
µA
µA
I
EBO
h
FE
V
CEsat
V
I(off)
V
I(on)
R1
R2/R1
C
c
PUML1_DG_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2008
5 of 12
stm32/stm8
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