CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
INPUT CHARACTERISTICS
R
IN
C
IN
Input Resistance
V
S
+ = 5V, V
S
- = GND, T
A
= +25°C, V
CM
= 2.5V, R
L
to 2.5V, A
V
= 1, Unless Otherwise Specified.
CONDITIONS
MIN
TYP
MAX
UNIT
DESCRIPTION
Common Mode
3.5
0.5
MΩ
pF
Input Capacitance
OUTPUT CHARACTERISTICS
R
OUT
I
OUT
Output Resistance
Linear Output Current
A
V
= +1
30
65
mΩ
mA
ENABLE (5962-0721301QXC ONLY)
t
EN
t
DS
V
IH-ENB
V
IL-ENB
Enable Time
Disable Time
ENABLE Pin Voltage for Power-up
ENABLE Pin Voltage for Shut-down
200
25
0.8
2
ns
ns
V
V
AC PERFORMANCE
BW
-3dB Bandwidth
A
V
= +1, R
F
= 0Ω, C
L
= 2.5pF
A
V
= -1, R
F
= 1kΩ, C
L
= 2.5pF
A
V
= +2, R
F
= 1kΩ, C
L
= 2.5pF
A
V
= +10, R
F
= 1kΩ, C
L
= 2.5pF
BW
Peak
GBWP
PM
SR
t
R
t
F
OS
t
PD
t
S
dG
dP
e
N
i
N
+
i
N
-
e
S
±0.1dB Bandwidth
Peaking
Gain Bandwidth Product
Phase Margin
Slew Rate
Rise Time
Fall Time
Overshoot
Propagation Delay
0.1% Settling Time
Differential Gain
Differential Phase
Input Noise Voltage
Positive Input Noise Current
Negative Input Noise Current
Channel Separation
R
L
= 1kΩ, C
L
= 2.5pF
A
V
= 2, R
L
= 100Ω, V
OUT
= 0.5V to 4.5V
2.5V
STEP
, 20% to 80%
2.5V
STEP
, 20% to 80%
200mV step
200mV step
200mV step
A
V
= +2, R
F
= 1kΩ, R
L
= 150Ω
A
V
= +2, R
F
= 1kΩ, R
L
= 150Ω
f = 10kHz
f = 10kHz
f = 10kHz
f = 100kHz
A
V
= +1, R
F
= 0Ω, C
L
= 2.5pF
A
V
= +1, R
L
= 1kΩ, C
L
= 2.5pF
500
140
165
18
35
2
200
55
600
4
2
10
1
15
0.01
0.01
12
1.7
1.3
95
MHz
MHz
MHz
MHz
MHz
dB
MHz
°
V/µs
ns
ns
%
ns
ns
%
°
nV/√Hz
pA/√Hz
pA/√Hz
dB
2
FN6478.1
October 17, 2007
5962-0721301QXC, 5962-0721302QXC, 5962-0721303QYC
Pin Descriptions
5962-0721301QXC
(10 LD FLATPACK)
1, 5
2, 4
3
6, 10
7, 9
8
3
6, 10
7, 9
8
2, 4
11
2, 6, 9, 13
1, 7, 8, 14
4
5962-0721302QXC
(10 LD FLATPACK)
1, 5
5962-0721303QYC
(14 LD FLATPACK)
3, 5, 10, 12
NAME
IN+
CE
VS-
IN-
OUT
VS+
NC
FUNCTION
Non-inverting input for each channel
Enable and disable input for each channel
Negative power supply
Inverting input for each channel
Amplifier output for each channel
Positive power supply
Not Connected
Simplified Schematic Diagram
V
S+
I
1
I
2
Q
5
R
3
R
1
IN+
Q
1
Q
2
R
2
IN-
DIFFERENTIAL TO
SINGLE ENDED
DRIVE
GENERATOR
Q
3
Q
4
Q
8
R
4
R
5
V
S-
R
9
OUT
R
6
R
7
V
BIAS1
R
8
Q
7
Q
6
V
BIAS2
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
3
FN6478.1
October 17, 2007
5962-0721301QXC, 5962-0721302QXC, 5962-0721303QYC
Ceramic Metal Seal Flatpack Packages (Flatpack)
K10.A
MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B)
e
-A-
b
PIN NO. 1
ID AREA
E1
0.004 M
H A-B S
D S
0.036 M
-B-
10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
A
D
INCHES
SYMBOL
A
b
b1
MIN
0.045
0.015
0.015
0.004
0.004
-
0.240
-
0.125
0.030
0.008
0.250
0.026
0.005
-
10
MAX
0.115
0.022
0.019
0.009
0.006
0.290
0.260
0.280
-
-
0.015
0.370
0.045
-
0.0015
MILLIMETERS
MIN
1.14
0.38
0.38
0.10
0.10
-
6.10
-
3.18
0.76
1.27 BSC
0.20
6.35
0.66
0.13
-
10
0.38
9.40
1.14
-
0.04
MAX
2.92
0.56
0.48
0.23
0.15
7.37
6.60
7.11
-
-
NOTES
-
-
-
-
-
3
-
3
-
7
-
2
-
8
6
-
-
Rev. 0 3/07
S1
H A-B S
D S
c
c1
D
E
E1
E2
E3
e
k
L
Q
S1
M
N
Q
A
-C-
E
C
-D-
-H-
L
E3
E2
E3
LEAD FINISH
L
SEATING AND
BASE PLANE
0.050 BSC
c1
BASE
METAL
b1
M
M
(b)
SECTION A-A
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
4
FN6478.1
October 17, 2007
5962-0721301QXC, 5962-0721302QXC, 5962-0721303QYC
14 ld FLATPACK Package Outline Drawing
A
K14.A
MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INCHES
SYMBOL
MIN
0.045
0.015
0.015
0.004
0.004
-
0.235
-
0.125
0.030
0.008
0.270
0.026
0.005
-
14
MAX
0.115
0.022
0.019
0.009
0.006
0.390
0.260
0.290
-
-
0.015
0.370
0.045
-
0.0015
A
b
b1
c
c1
D
MILLIMETERS
MIN
1.14
0.38
0.38
0.10
0.10
-
5.97
-
3.18
0.76
1.27 BSC
0.20
6.86
0.66
0.13
-
14
0.38
9.40
1.14
-
0.04
MAX
2.92
0.56
0.48
0.23
0.15
9.91
6.60
7.11
-
-
NOTES
-
-
-
-
-
3
-
3
-
7
-
2
-
8
6
-
-
Rev. 0 5/18/94
e
PIN NO. 1
ID AREA
A
-A-
-B-
D
S1
b
E1
0.004 M
Q
A
-C-
-H-
L
E3
SEATING AND
BASE PLANE
c1
LEAD FINISH
E2
E3
L
H A-B S
D S
E
0.036 M
H A-B S
C
-D-
D S
E
E1
E2
E3
e
k
L
Q
S1
M
N
0.050 BSC
BASE
METAL
b1
M
M
(b)
SECTION A-A
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
FPGA/CPLD
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