BU-61590
MIL-STD-1553A/B AND McAIR BC/RT/MT,
ADVANCED COMMUNICATION ENGINE (ACE)
FEATURES
•
Fully Integrated Terminal
DESCRIPTION
DDC's
BU-61590
BC/RT/MT
Universal Advanced Communication
Engine (ACE) terminal comprises a
complete integrated interface between
a host processor and a MIL-STD-
1553, STANAG 3838, or McAir bus.
The BU-61590 integrates a dual uni-
versal McAir transceiver, protocol,
memory management and processor
interface logic, and 4K words of inter-
nal buffered RAM in either a 78-pin
DIP or flat pack package.
This dual universal transceiver provides
a sinusoidal waveform for full compli-
ance with 1553A, 1553B, and McAir
A3818, A5232, and A5690 standards.
To minimize board space and "glue"
logic, the Universal ACE terminals
provide the ultimate flexibility in inter-
facing to a host processor and inter-
nal/external RAM.
The BU-61590 provides complete
multiprotocol support of MIL-STD-
1553A, 1553B Notice 2, McAir A3818,
A5232,
and
A5690,
General
Dynamics
16PP303,
Grumman
SPG151A, and STANAG 3838 (includ-
ing EFAbus). The advanced functional
architecture of the ACE terminals pro-
vides software compatibility to DDC's
previous AIM series hybrids. In addi-
tion, the ACE Terminals incorporate a
multiplicity of architectural enhance-
ments allowing flexible operation while
off-loading the host processor, ensur-
ing data consistency, and supporting
bulk data transfers.
The BU-61590 may be operated at
either 12 or 16 MHz. Options allow for
a hardwired or programmable RT
address.
The BU-61590 operates over the full
military temperature range of -55 to
+125°C. Available screened to MIL-
PRF-38534, the terminals are ideal
for demanding military and industrial
processor-to-1553 applications.
•
Dual Universal Transceiver
Satisfies McAir and 1553A/B
•
Multiprotocol Supports:
MIL-STD-1553A and B Notice 2
McAir A3818, A5232, & A5690
General Dynamics 16PP303
(F16) Grumman SPG151A
•
4K x 16 Internal RAM
•
Flexible Processor/Memory
Interface
•
Automatic BC Retries
•
Programmable BC Gap Times
•
BC Frame Auto-Repeat
•
Flexible RT Data Buffering
•
Programmable Illegalization
•
Selective Message Monitor
•
Simultaneous RT/Monitor Mode
TX/RX_A
4K X 16
SHARED
RAM
TRANSCEIVER
A
DATA
BUFFERS
PROCESSOR
DATA BUS
CH. A
TX/RX_A
DATA BUS
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
D15-D0
TX/RX_B
ADDRESS BUS
ADDRESS
BUFFERS
A15-A0
PROCESSOR
ADDRESS BUS
CH. B
TRANSCEIVER
B
TX/RX_B
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT, INT_ACK
IOEN, MEMENA-OUT, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
RT ADDRESS
RTAD4-RTAD0, RTADP
INCMD
MISCELLANEOUS
CLK_IN, TAG_CLK, BC/MT_ENA, TX_INH_A, TX_INH_B,
MSTCLR, SSFLAG/EXT_TRG, ILLEGAL, RT_AD_LAT
BU-61590 BLOCK DIAGRAM
©
1994, 1999 Data Device Corporation
BU-61590 SERIES SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
n
Logic +5 V
n
Transceiver +5 V
n
Transceiver +V
n
Transceiver -V
Logic
n
Voltage Input Range
RECEIVER
Differential Input Resistance (Note 1)
Differential Input Capacitance (Note1)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 2)
TRANSMlTTER
Differential Output Voltage
n
Direct Coupled Across 35 Ohms,
Measured on Bus
n
Transformer Coupled, Measured
on Stub
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Direct
Coupled Across 35 Ohms
Rise/Fall Time
LOGIC
V
IH
V
lL
I
IH
(V
CC
=5.5 V, V
IN
=5.0 V)
I
IH
(V
CC
=5.5 V, V
IN
=2.4 V)
n
SSFLAG/EXT_TRIG
n
All Other Inputs
I
IL
(V
CC
=5.5 V, V
IN
=0 V)
n
SSFLAG/EXT_TRIG
n
All Other Inputs
V
OH
(V
CC
=4.5 V, V
IH
=2.4 V, V
IL
=0.7
V, l
OH
=max)
V
OL
(V
CC
=4.5 V, V
IH
=2.4 V, V
lL
=0.7
V, I
OL
=max)
I
OL
n
(DB0-DB15, A0-A15,
MEMOE/ADDR_LAT,
MEMWR/ZEROWAIT,
DTREQ 16/8, DTACK/POLARI
TY_SEL
n
INCMD, INT, MEMENA_OUT,
READYD, IOEN
I
OH
n
(DB0-DB15, A0-A15,
MEMOE/ADDR_LAT,
MEMWR/ZEROWAIT,
DTREQ/16/8, DTACK/POLARI-
TY_SEL)
n
INCMD, INT, MEMENA_OUT,
READYD, IOEN
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
n
+5 V (Logic)
n
+5 V (CH. A CH. B)
n
+V (CH. A CH. B)
n
-V (CH. A CH. B)
Current Drain (Total Hybrid)
n
+5 V
n
+V (+12 V to +15 V)
• Idle
• 25% Duty Cycle
• 50% Duty Cycle
• 100% Dutv Cycle
MIN
TYP
MAX
UNITS
BU-61590 SERIES SPECIFICATIONS
(contd)
PARAMETER
n
-V (-12V to -15V)
• Idle
• 25% Duty Cycle
• 50% Duty Cycle
• 100% Dutv Cycle
POWER DISSIPATION
Total Hybrid
n
Idle
n
25% Duty Cycle
n
50% Duty Cycle
n
100% Duty Cycle
Hottest Die
n
Idle
n
25% Duty Cycle
n
50% Duty Cycle
n
100% Dutv Cycle
CLOCK INPUT
Frequency
n
Nominal Value (programmable)
• default
• option
n
Long Term Tolerance
• 1553A Compliance
• 1553B Compliance
n
Short Term Tolerance 1 second
• 1553A Compliance
• 1553B Compliance
n
Duty Cycle
• 16MHz
• 12MHz
1553 MESSAGE TIMING
RT Response Time
(mid-parity to mid-sync)
Completion of CPU Write (BC Start-
to-Start of First BC Message)
BC Intermessage Gap (Note 2)
BC/RT/MT Response Timeout(Note 3)
n
18.5 nominal
n
22.5 nominal
n
50.5 nominal
n
128.0 nominal
Trasnmitter Watchdog Timeout
THERMAL
Thermal Resistance Junction-to-
Case Hottest Die (θJC)
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering 10 sec-
onds)
PHYSICAL CHARACTERISTICS
Size
n
78-pin DIP, Flat Pack
Weight
n
78-pin DIP. Flat Pack
MIN
TYP
28
55
81
134
MAX UNITS
60
86
112
165
mA
mA
mA
mA
-0.3
-0.5
-0.3
+0.3
-0.3
6
7.0
7.0
+18.0
-18.0
V
CC
+0.3
V
V
V
V
V
kOhm
pF
V
p-p
V
peak
10
0.860
10
1.31
1.81
2.28
3.24
2.50
2.97
3.45
4.40
W
W
W
W
W
W
W
W
0
0.045 0.072
0.095 0.143
0.205 0.287
6
18
7
20
9
27
10
Vp-p
mVp-p, diff
mV
nsec
V
V
µA
µA
µA
µA
µA
V
V
mA
16.0
12.0
0.01
0.1
0.001
0.01
33
40
4
2.5
9.5
17.5
21.5
49.5
127
18.5
22.5
50.5
128
668
19.5
23.5
51.5
129
7
67
60
MHz
MHz
%
%
%
%
%
%
µs
µs
µs
µs
µs
µs
µs
µs
°C/W
°C
°C
°C
-90
280
2.0
-10
-692
-346
-794
-397
2.4
90
300
0.8
10
-84
-42
-100
-50
0.4
6.4
67.23
-55
-65
160
150
+300
3.2
mA
-6.4
mA
-3.2
mA
2.1 x 1.8 x 0.210
in
(53.34 x 45.72 x 5.33) (mm)
1.0
(29)
oz
(g)
4.5
4.5
11.4
-
15.75
95
28
55
81
134
5.5
5.5
15.75
-11.4
190
60
86
112
165
V
V
V
V
mA
mA
mA
mA
mA
Notes:
1. Specifications include both transmitter and receiver (tied together internally).
Measurement of impedance is directly between pins TX/RX A(B) and TX/RX
A(B) of the BU-61590X5 hybrid. Assuming the connection of all power and
ground inputs to the hybrid. The specifications are applicable for both unpow-
ered and powered conditions. The specifications assume a 2 volt rms balanced
differential, sinusoidal input. The applicable frequency range is 75 kHz to 1
MHz. Minimum resistance and maximum capacitance parameters are guaran-
teed, but not tested, over the operating range.
2. Typical value for minimum intermessage gap time. Under software conlrol, may
be lengthened to (65,535 µs minus message time), in increments of 1 µs.
3. Software programmable (4 options). Includes RT-to-RT Timeout (Mid-Parity of
Transmit Command to Mid-Sync of Transmitting RT Status).
2
BU-61590 PIN LISTING (78-PIN DIP OR FLAT PACK)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
TX/RX-A
TX/RX-A
GNDA
TX_INH_A
SELECT
STRBD
MEM_REG
RD/WR
MSTCLR
A15
A14
A13
A12
A11
A10
A09
A08
LOGIC GND
+5 V LOGIC
A07
A06
A05
A04
A03
A02
A01
NAME
PIN
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
A00
DTGRT/MSB/LSB
SSFLAG/EXT_TRIG
MEMENA_OUT
MEMOE/ADDR_LAT
MEMWR/ZERO_WAIT
DTREQ/16/8
DTACK/POLARITY_SEL
MEMENA_IN/TRIGGER_SEL
ILLEGAL
TX/RX-B
TX/RX-B
GNDB
+5 VB
-15 VB
+15 VB
CLOCK_IN
RT_AD_LAT
RTAD0
RTAD1
RTAD2
RTAD3
RTAD4
RTADP
INCMD
D00
NAME
PIN
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
TAG_CLK
TRANSPARENT/BUFFERED
INT
READYD
IOEN
INT_ACK
BC/MT_ENA
TX_INH_B
+5 VA
-15 A
+15 A
NAME
0.210
MAX
(5.33)
2.100 MAX
(53.34)
PIN NUMBERS FOR
REFERENCE ONLY
40
41
78
77
1.500
(38.1)
1
1.650
(41.91)
1
1.800 MAX
(45.72)
34
35
2
1
0.100 TYP (2.54)
0.050 TYP (1.27)
SEE DETAIL "A"
1
1.800 (45.72)
1.900 (48.26)
1
INDEX
DENOTES
PIN 1
2
0.018 ±0.002 DIA TYP
(0.46 ±0.05)
0.250 ±0.010
(6.35 ±0.25)
NOTES:
1 LEAD CLUSTER TO BE LOCATED WITH
±0.005 (±0.127) OF CASE CENTER LINE.
2 CERAMIC PACKAGE KOVAR COVER.
3. DIMENSIONS ARE IN INCHES (mm).
DETAIL "A"
BU-61590DX, 78-PIN DIP PACKAGE, MECHANICAL OUTLINE
3
PN 1 DENOTED
BY INDEX TAB
ON LEAD BRAZE
1.800 MAX
(45.72)
0.400 MIN TYP
(10.16)
78
1
2.100 MAX
(53.34)
38 EQ. SP. @
0.050 = 1.90
TOL NONCUM
(1.27 = 48.26)
1
2
0.018 ±0.002 TYP
(0.46 ±0.05)
DETAIL "A"
39
40
PIN NUMBERS FOR
REFERENCE ONLY
0.050 TYP
(1.27)
SEE DETAIL "A"
NOTES:
1
LEAD CLUSTER TO BE LOCATED WITH
±0.005 (±0.13) OF CASE CENTER LINE.
2
CERAMIC PACKAGE KOVAR COVER.
3.DIMENSIONS ARE IN INCHES (mm).
0.100 ±0.010 TYP
(2.54 ±0.25)
0.210 MAX (5.33)
0.010 ±0.002 TYP
(0.25 ±0.05)
FIGURE 3. BU-61590FX, 78-PIN FLAT PACK PACKAGE, MECHANICAL OUTLINE
4
ORDERING INFORMATION
BU-61590XX-XX0X
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
K = One Lot Date Code
W = One Lot Date Code and PreCap Source
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, PreCap Source and 100% Pull Test
Blank = None of the Above
Process Requirements:
0 = Standard DDC Processing, no Burn-In
1 = MIL-PRF-38534 Compliant
2 = B*
3 = MIL-PRF-38534 Compliant with PIND Testing
4 = MIL-PRF-38534 Compliant with Solder Dip
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
6 = B* with PIND Testing
7 = B* with Solder Dip
8 = B* with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In
Temperature Grade/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
8 = 0°C to +70°C with Variables Test Data
Voltage Transceiver Option:
5 = +5/+15/-15 V Sinusoidal (McAir)
Package:
D = DIP
F = Flat Pack
Product Type:
61590 = 78-Pin BC/RT/MT with 4K RAM
*Standard DDC Processing with burn-in and full temperature test.
5
stm32/stm8
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