SwitchStar
TM
Switch Manager
IDT77V550
Features List
Interprets switch command cells from external work station
and loads the command into the IDT77V500 Switch
Controller
u
Utilizes in-stream (in-band) signalling technique via the cell
stream into the Switching Memory
u
Can generate control cells to be sent back to the external
workstation
u
Executes three types of commands:
– Writing data to Switch Controller
– Reading data from Switch Controller
– Reset operations
u
Single +3.3V ± 0.3V power supply
u
Industrial Temperature (-40°C to 85°C) is available.
u
IDT77V550 is located on the IDT77V400 port to receive both signalling
cells and standard traffic cells. The Switch Manager does not have to be
connected to a Switching Memory port if it is only receiving the signalling
cells.
The Switch Manager has two cell streams which flow in opposite
directions, and can both interpret an incoming cell and generate control
cells as necessary. Figure 2 illustrates the basic block configuration of
the Switch Manager. The Data Path Interface (DPI) is used on both the
cell input and output ports of the IDT77V550. DPI is utilized on the
IDT77V400 to provide both reduced pin count per port and to offer
configuration flexibility.
The IDT77V550 is capable of executing four basic types of
commands in the system:
u
Writing data to the Switch Controller
u
Reading data from the Switch Controller
u
Resetting the switch components
u
Reading Switch Manager version information
When writing information to the Switch Controller, the IDT77V550 will
store information needed to execute the command (up to 32 bytes) in
internal memory and perform the command across the Switch Controller
Manager bus. Likewise, for a read operation the information is received
from the Switch Controller, stored internally by the IDT77V550, and then
Description
The IDT77V550 Switch Manager is a device developed to provide a
simple method of communication between an external workstation/
processor and the IDT77V500 Switch Controller. An In-Band signalling
technique is utilized to examine incoming ATM cells, determining if the
cell is a Command Cell for the Switch Controller, and loads the
command if appropriate. In the typical configuration (Figure 1), the
Block Diagram
Line Cards
DPI Receive
DPI Transmit
Switching Memory
,
•
•
•
Switch Manager
DPI Receive
DPI Receive
IDT77V550
DPI Transmit
DPI Transmit
Control Bus
Switch Controller
4523 drw 01
Figure 1 IDT77V550 Application with IDT77V400 Switching Memory and IDT77V500 Switch Controller
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©
2000 Integrated Device Technology, Inc.
IDT77V500
IDT77V400
June 22, 2001
DSC 5917
IDT77V550
transmitted to the external workstation via a generated cell. Please refer
to the data sheet of the IDT77V500 Switch Controller and the SwitchStar
User Manual for additional information on these commands.
Additional information on DPI is available in Technical Note 34 on
the IDT Web Site at:
http://www.idt.com/products/pages/ATM-PL114_Sub227_Dev285.html.
The switch command cell enters the Switch Manager at the Port DPI
input interface, and they are interpreted in the cell receiver. If the
received cell VPI/VCI address matches the VPI/VCI expected for a
command cell the Switch Manager begins executing the command. The
switch command cell is filtered out by the Switch Manager.
For a write data switch command to the Switch Controller, the
internal cell receiver of the IDT77V550 stores up to 32 data bytes to
internal memory. Then the IDT77V550 writes the data to the IDT77V500
Switch Controller using the eight bit Manager bus interface. Finally the
Switch Manager will write the switch control instruction to the instruction
register in the Switch Controller.
For a read data switch command to the Switch Controller, the Switch
Manager reads the appropriate number of the bytes and stores them
internally. The data is returned to the external control source on the
lower cell stream of the port (see Figure 2). The cell generator will look
for a space in the cell stream before stopping the DPI read clock and
inserting the Switch Manager generated cell.
The switch manager can only process one command cell at a time.
Each command cell received by the switch manager must be processed
prior to receiving another command cell.
Once the IDT77V550 is finished processing the command cell, it will
drive the Manager Bus based on the command received. It is necessary
to wait for an acknowledgment from the IDT77V500 Switch Controller
that the command sent by the IDT77V550 has been received and
processed by the IDT77V500. Acknowledgment means the IDT77V500
sets MDATA 7 high after a command has been executed. The
IDT77V550 can not receive or process another command cell until it
receives this acknowledgment from the IDT77V500.
Revision History
February 15, 1999:
Initial publication.
September 2, 1999:
Added line to paragraph in DPI Receive Path.
Changed name of table to Command Field format and added informa-
tion and note. Changed waveforms to include SCLK.
February 4, 2000:
Changed pin in Pin Configuration diagram.
Changed pin definitions in Pin definitions table. Changed data in several
tables. Made changes to Table 23, AC Electrical Characteristics. Made
changes to Order Information section.
March 24, 2000:
Made changes to last paragraph in Device Opera-
tions section. Made changes in last row of Table 23, AC Electrical Char-
acteristics. Edited timing waveforms and added new waveform.
July 28, 2000:
Added paragraph to Device Operation section. Added
information in Switch Manager Commands section. Deleted tRESTED
row in Table 23. Deleted Command Cell Execution Delay Timing Wave-
form.
November 2, 2000:
Updated QFP80 Package and made several
minor edits.
March 26, 2001:
Corrected package dimensions (Note 3 for Figure
3) to read 12 mm x 12 mm x 1.4 mm.
June 22, 2001:
Added a Note 6 to Figure 9 and another Note 6 to
Figure 10. Removed “All resets will be asserted by the Switch Manager
for at least 1.5us” from Reset Operations section.
DPI
DPI input Port
Input
DPI
Output
DPI output to Switching Memory
I/F
Cell receiver
I/F
Memory
Mgr
R/W
controller
Control bus for Switch Controller
I/F
Cell generator
,
DPI
Input
DPI output Port
DPI
Output
DPI input from Switching Memory
I/F
I/F
4523 drw 02
Figure 2 Basic Block Configuration of the Switch Manager
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IDT77V550
Pin Configurations
V
SS
V
CC
RESETO
RESETO
CS
V
SS
V
CC
OCLK
M
OFRM
M
OPD
3M
OPD
2M
OPD
1M
OPD
0M
CTLEN
INDEX
79
78
77
76
70
69
75
72
71
68
67
66
65
64
63
62
80
74
73
61
OCLK
OFRM
V
SS
V
SS
V
CC
OE
SCLK
V
CC
V
SS
RESETI
RESETP
0
RESETP
1
RESETP
2
RESETP
3
V
CC
RESETP
4
RESETP
5
RESETP
6
RESETP
7
V
SS
IPD
0
IPD
1
IPD
2
IPD
3
IFRM
ICLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
60
59
58
57
56
55
54
OPD
3
OPD
2
V
CC
OPD
1
OPD
0
V
SS
V
CC
SWAD
7
SWAD
6
SWAD
5
SWAD
4
V
SS
SWAD
3
SWAD
2
SWAD
1
SWAD
0
V
CC
MSTRB
MR/W
MD/C
,
IDT77V550
PN80-2(4)
80-Pin TQFP
Top View(5)
53
52
51
50
49
48
47
46
45
44
43
42
21
27
28
30
31
33
34
26
35
36
37
38
24
25
29
32
39
40
20
22
23
41
MDATA
1
MDATA
2
MDATA
5
MDATA
6
MDATA
3
V
CC
Figure 3 Pin Configuration
Note:
1.All VCC pins must be connected to power supply.
2.All VSS pins must be connected to ground supply.
3.Package body is approximately 12 mm x 12 mm x 1.4 mm.
4.This package code is used to reference the package diagram.
5.This text does not indicate orientation of the actual part marking.
6.OCLK pin 83 is associated with OFRM pin 61 (to external control); OCLKM pin 62 is associated with pin 82
(from Switching Memory).
7.NC represents No Connection; these pins should not be connected to either VCC or VSS.
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MDATA
0
MDATA
4
MDATA
7
V
SS
V
CC
V
SS
IPD
0M
IPD
1M
IPD
2M
IPD
3M
IFRM
M
ICLK
M
V
CC
V
SS
45234 drw 03a
June 22, 2001
IDT77V550
Pin Definitions
Pin Number
1
4
68
69
5
6
7
8
10
11
12
13
45
46
47
48
50
51
52
53
41
42
43
31
32
33
34
36
37
38
39
15
16
17
18
19
Symbol
SCLK
RESETI
RESETO
RESETO
RESETP0
RESETP1
RESETP2
RESETP3
RESETP4
RESETP5
RESETP6
RESETP7
SWAD0
SWAD1
SWAD2
SWAD3
SWAD4
SWAD5
SWAD6
SWAD7
MD/C
MR/W
MSTRB
MDATA0
MDATA1
MDATA2
MDATA3
MDATA4
MDATA5
MDATA6
MDATA7
IPD0
IPD1
IPD2
IPD3
IFRM
Type
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Input
Input
Input
40 MHz system clock.
Reset input. Active low.
Reset output. Active low.
Reset output. Active high.
Reset output to port number 0. Active low.
Reset output to port number 1. Active low.
Reset output to port number 2. Active low.
Reset output to port number 3. Active low.
Reset output to port number 4. Active low.
Reset output to port number 5. Active low.
Reset output to port number 6. Active low.
Reset output to port number 7. Active low.
Switch VCI address. LSB.
Switch VCI address.
Switch VCI address.
Switch VCI address.
Switch VCI address.
Switch VCI address.
Switch VCI address.
Switch VCI address. MSB.
Control bus. Selector for accessing data or control word.
Control bus. Selector for read or write operation.
Control bus. Master strobe. Latching on positive edge.
Control bus. Data bus to Switch Controller. LSB.
Control bus. Data bus to Switch Controller.
Control bus. Data bus to Switch Controller.
Control bus. Data bus to Switch Controller.
Control bus. Data bus to Switch Controller.
Control bus. Data bus to Switch Controller.
Control bus. Data bus to Switch Controller.
Control bus. Data bus to Switch Controller. MSB.
DPI to Switch Manager interface. Data bus.
DPI to Switch Manager interface. Data bus.
DPI to Switch Manager interface. Data bus.
DPI to Switch Manager interface. Data bus.
Linecard to Switch Manager DPI interface. New frame.
Description
Table 1 Pin Descriptions (Part 1 of 2)
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June 22, 2001
IDT77V550
Pin Number
20
23
24
25
26
27
28
56
57
59
60
61
62
72
73
74
75
76
77
67
66
65
2,9,21,29,35,44,
54,58,63,70,78
3,14,22,30,40,49,
55,64,71,79,80
Symbol
ICLK
IPD0M
IPD1M
IPD2M
IPD3M
IFRMM
ICLKM
OPD0
OPD1
OPD2
OPD3
OFRM
OCLK
OPD0M
OPD1M
OPD2M
OPD3M
OFRMM
OCLKM
CS
OE
CTLEN
VCC
VSS
Type
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Power
GND
Description
Linecard to Switch Manager DPI interface. Data clock connect.
Switch Manager to Switching Memory DPI interface. Data bus.
Switch Manager to Switching Memory DPI interface. Data bus.
Switch Manager to Switching Memory DPI interface. Data bus.
Switch Manager to Switching Memory DPI interface. Data bus.
Switch Manager to Switching Memory DPI interface. New frame.
Switch Manager to Switching Memory DPI interface. Data clock.
Switch Manager to DPI interface. Data bus.
Switch Manager to DPI interface. Data bus.
Switch Manager to DPI interface. Data bus.
Switch Manager to DPI interface. Data bus.
Switch Manager to DPI interface. New frame.
Switch Manager to DPI interface. Data clock.
Switching Memory to Switch Manager DPI interface. Data bus.
Switching Memory to Switch Manager DPI interface. Data bus.
Switching Memory to Switch Manager DPI interface. Data bus.
Switching Memory to Switch Manager DPI interface. Data bus.
Switching Memory to Switch Manager DPI interface. New frame.
Switching Memory to Switch Manager DPI interface. Data clock.
Chip select for 77V400 Switching Memory.
Output enable for 77V400 Switching Memory.
Control Enable for 77V400 Switching Memory.
3.3V Power Supply Pins.
Ground Pins
Table 1 Pin Descriptions (Part 2 of 2)
Absolute Maximum Ratings
(1)
Symbol
VTERM
(2)
TBIAS
TSTG
IOUT
Rating
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
DC Output Current
Table 2 Ratings
Commercial & Industrial
-0.5 to +3.9
-55 to +125
-65 to +150
20
Unit
V
°C
°C
mA
Note:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2.VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period
of VTERM > Vcc + 0.3V.
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June 22, 2001
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