SN54HCT08, SN74HCT08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCLS063B – NOVEMBER 1988 – REVISED MAY 1997
D
D
Inputs Are TTL-Voltage Compatible
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
SN54HCT08 . . . J OR W PACKAGE
SN74HCT08 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
description
These devices contain four independent 2-input
AND gates. They perform the Boolean function
Y
A
•
B or Y
A B in positive logic.
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4B
4A
4Y
3B
3A
3Y
+
+ )
The SN54HCT08 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HCT08 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
H
L
L
SN54HCT08 . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
V
CC
4B
1Y
NC
2A
NC
2B
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
4A
NC
4Y
NC
3B
NC – No internal connection
logic symbol
†
1A
1B
2A
2B
3A
3B
4A
4B
1
2
4
5
9
10
12
13
11
4Y
8
3Y
6
2Y
&
3
1Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
logic diagram (positive logic)
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
©
1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
2Y
GND
NC
3Y
3A
1
SN54HCT08, SN74HCT08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCLS063B – NOVEMBER 1988 – REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54HCT08
MIN
VCC
VIH
VIL
VI
VO
tt
TA
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
Input transition (rise and fall) time
Operating free-air temperature
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
4.5
2
0
0
0
0
–55
0.8
VCC
VCC
500
125
NOM
5
MAX
5.5
SN74HCT08
MIN
4.5
2
0
0
0
0
–40
0.8
VCC
VCC
500
85
NOM
5
MAX
5.5
UNIT
V
V
V
V
V
ns
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
II
ICC
∆I
CC‡
Ci
TEST CONDITIONS
VI = VIH or VIL
VI = VIH or VIL
VI = VCC or 0
VI = VCC or 0,
IOH = –20
µA
IOH = –4 mA
IOL = 20
µA
IOL = 4 mA
VCC
4.5
45V
4.5
45V
5.5 V
5.5 V
5.5 V
4.5 V
to 5.5 V
1.4
3
TA = 25°C
MIN
TYP
MAX
4.4
3.98
4.499
4.3
0.001
0.17
±0.1
0.1
0.26
±100
2
2.4
10
SN54HCT08
MIN
4.4
3.7
0.1
0.4
±1000
40
3
10
MAX
SN74HCT08
MIN
4.4
3.84
0.1
0.33
±1000
20
2.9
10
MAX
UNIT
V
V
nA
µA
mA
pF
IO = 0
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2
POST OFFICE BOX 655303
•
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SN54HCT08, SN74HCT08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCLS063B – NOVEMBER 1988 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
d
tt
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
Y
VCC
4.5 V
5.5 V
4.5 V
5.5 V
TA = 25°C
MIN
TYP
MAX
15
13
9
8
24
22
15
14
SN54HCT08
MIN
MAX
35
32
22
20
SN74HCT08
MIN
MAX
30
27
19
17
UNIT
ns
ns
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance per gate
TEST CONDITIONS
No load
TYP
20
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
In-Phase
Output
3V
Input
1.3 V
tPLH
1.3 V
10%
tPHL
Out-of-Phase
Output
90%
1.3 V
10%
tf
90%
tr
Input 1.3 V
0.3 V
2.7 V
2.7 V
3V
1.3 V
0.3 V 0 V
tf
tPLH
1.3 V
10%
90%
tr
VOH
VOL
1.3 V
0V
tPHL
90%
VOH
1.3 V
10% V
OL
tf
LOAD CIRCUIT
tr
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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Copyright
©
1998, Texas Instruments Incorporated
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PRODUCT SUPPORT:
TRAINING
SN74HCT08, Quadruple 2-Input Positive-AND Gates
DEVICE STATUS:
ACTIVE
PARAMETER NAME SN74HCT08
Voltage Nodes (V)
Vcc range (V)
Input Level
Output Level
5
4.5 to 5.5
TTL
CMOS
Output Drive (mA) -4/4
No. of Gates
Static Current
tpd max (ns)
4
0.02
27
FEATURES
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q
q
Inputs Are TTL-Voltage Compatible
Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard
Plastic (N) and Ceramic (J) 300-mil DIPs
DESCRIPTION
Back to Top
These devices contain four independent 2-input AND gates. They perform the Boolean function
or
in positive logic.
The SN54HCT08 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74HCT08 is characterized for operation from -40°C to 85°C.
TECHNICAL DOCUMENTS
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DATASHEET
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Full datasheet in Acrobat PDF:
sn74hct08.pdf
(77 KB,Rev.B) (
Updated: 05/01/1997
)
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