电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

CD4015CW

产品描述Serial In Parallel Out, 4000/14000/40000 Series, 4-Bit, Right Direction, True Output, WAFER
产品类别逻辑    逻辑   
文件大小55KB,共6页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
下载文档 详细参数 全文预览

CD4015CW概述

Serial In Parallel Out, 4000/14000/40000 Series, 4-Bit, Right Direction, True Output, WAFER

CD4015CW规格参数

参数名称属性值
厂商名称Fairchild
零件包装代码WAFER
包装说明DIE,
Reach Compliance Codeunknown
计数方向RIGHT
系列4000/14000/40000
JESD-30 代码X-XUUC-N16
逻辑集成电路类型SERIAL IN PARALLEL OUT
位数4
功能数量2
端子数量16
输出极性TRUE
封装主体材料UNSPECIFIED
封装代码DIE
封装形状UNSPECIFIED
封装形式UNCASED CHIP
传播延迟(tpd)350 ns
认证状态Not Qualified
最大供电电压 (Vsup)15 V
最小供电电压 (Vsup)3 V
标称供电电压 (Vsup)5 V
表面贴装YES
端子形式NO LEAD
端子位置UPPER
触发器类型POSITIVE EDGE
最小 fmax2 MHz

CD4015CW文档预览

CD4015BC Dual 4-Bit Static Shift Register
October 1987
Revised January 1999
CD4015BC
Dual 4-Bit Static Shift Register
General Description
The CD4015BC contains two identical, 4-stage, serial-
input/parallel-output registers with independent “Data”,
“Clock,” and “Reset” inputs. The logic level present at the
input of each stage is transferred to the output of that stage
at each positive-going clock transition. A logic high on the
“Reset” input resets all four stages covered by that input.
All inputs are protected from static discharge by a series
resistor and diode clamps to V
DD
and V
SS
.
Features
s
Wide supply voltage range:
s
High noise immunity:
compatibility:
3.0V to 18V
0.45 V
DD
(typ.)
s
Low power TTL: Fan out of 2 driving 74L
or 1 driving 74LS
s
Medium speed operation: 8 MHz (typ.) clock rate
s
Fully static design: @V
DD
V
SS
=
10V
Applications
• Serial-input/parallel-output data queueing
• Serial to parallel data conversion
• General purpose register
Ordering Code:
Order Number
CD4015BCM
CD4015BCN
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Truth Table
CL
(Note 1)
D
0
1
X
X
R
0
0
0
1



X
Q
1
0
1
Q
1
0
Q
n
Q
n−1
Q
n−1
Q
n
0
(No change)
X
=
Don't Care Case
Note 1:
Level Change
© 1999 Fairchild Semiconductor Corporation
DS005948.prf
www.fairchildsemi.com
CD4015BC
Logic Diagrams
Terminal No. 16
=
V
DD
Terminal No. 8
=
GND
www.fairchildsemi.com
2
CD4015BC
Absolute Maximum Ratings
(Note 2)
(Note 3)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temperature Range (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260°C
700 mW
500 mW
−0.5
to
+18
V
DC
−0.5
to V
DD
+0.5
V
DC
−65°C
to
+150°C
Recommended Operating
Conditions
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range (T
A
)
+3
to
+15
V
DC
0 to V
DD
V
DC
−40°C
to
+85°C
Note 2:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be operated at these limits. The tables of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provide con-
ditions for actual device operation.
Note 3:
V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
(Note 3)
Symbol
I
DD
Parameter
Quiescent Device
Current
V
OL
LOW Level
Output Voltage
V
OH
HIGH Level
Output Voltage
V
IL
LOW Level
Input Voltage
V
IH
HIGH Level
Input Voltage
I
OL
LOW Level Output
Current (Note 4)
I
OH
HIGH Level Output
Current (Note 4)
I
IN
Input Current
Conditions
V
DD
=
5V, V
IN
=
V
DD
or V
SS
V
DD
=
10V, V
IN
=
V
DD
or V
SS
V
DD
=
15V, V
IN
=
V
DD
or V
SS
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1.0V or 9.0V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1.0V or 9.0V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
DD
=
5V, V
O
=
0.4V
V
DD
=
10V, V
O
=
0.5V
V
DD
=
15V, V
O
=
1.5V
V
DD
=
5V, V
O
=
4.6V
V
DD
=
10V, V
O
=
9.5V
V
DD
=
15V, V
O
=
13.5V
V
DD
=
15V, V
IN
=
0V
V
DD
=
15V, V
IN
=
15V
Note 4:
I
OH
and I
OL
are tested one output at a time.
−40°C
Min
Max
20
40
80
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.52
1.3
3.6
−0.52
−1.3
−3.6
−0.3
0.3
3.5
7.0
11.0
0.44
1.1
3.0
−0.44
−1.1
−3.0
4.95
9.95
14.95
Min
+25°C
Typ
0.005
0.010
0.015
0
0
0
5
10
15
2.25
4.50
6.75
2.75
5.50
8.25
0.88
2.25
8.8
−0.88
−2.25
−8.8
−10
−5
+85°C
Max
20
40
80
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.36
0.9
2.4
−0.36
−0.9
−2.4
−0.3
0.3
−1.0
1.0
1.5
3.0
4.0
Min
Max
150
300
600
0.05
0.05
0.05
Units
µA
µA
µA
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
µA
µA
10
−5
3
www.fairchildsemi.com
CD4015BC
AC Electrical Characteristics
Symbol
CLOCK OPERATION
t
PHL
, t
PLH
Propagation Delay Time
Parameter
(Note 5)
Conditions
Min
Typ
Max
Units
T
A
=
25
°
C, C
L
=
50 pF, R
L
=
200k, t
r
=
t
f
=
20 ns, unless otherwise specified
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
230
80
60
100
50
40
160
60
50
350
160
120
200
100
80
250
110
85
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
MHz
MHz
MHz
t
THL
, t
TLH
Transition Time
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
t
WL
, t
WM
Minimum Clock
Pulse-Width
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Clock Input
Other Inputs
2
4.5
6
t
rCL
, t
fCL
Clock Rise and
Fall Time
t
SU
Minimum Data
Set-Up Time
50
20
15
3.5
8
11
7.5
5
200
100
80
135
40
30
100
40
30
f
CL
Maximum Clock
Frequency
C
IN
RESET OPERATION
t
PHL(R)
Input Capacitance
10
7.5
400
200
160
250
80
60
pF
pF
ns
ns
ns
ns
ns
ns
Propagation Delay Time
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
t
WH(R)
Minimum Reset
Pulse Width
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Note 5:
AC Parameters are guaranteed by DC correlated testing.
www.fairchildsemi.com
4
CD4015BC
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
5
www.fairchildsemi.com
一种新的用于射频功率放大器的预失真器
作者:同济大学 电信学院 刘战胜 贾建华 在各种射频功率放大器线性化技术中,前馈技术有很高的线性度和带宽,但是其电路结构复杂,成本昂贵,而且效率低,他主要用于大功率放大器中,在直放站中 ......
fighting 模拟电子
基于FPGA的DA数模转换
如何在FPGA上设计DA数模转换电路?(就是在FPGA的芯片上实现DA转换功能)求大侠们给小弟说一下! 本帖最后由 非图后来之福报 于 2011-7-21 17:37 编辑 ]...
非图后来之福报 FPGA/CPLD
STEVAL-IDB007V1RSSI值与距离关系测试1
还没有修改APP,之前用官方的App测试下RSSI值;后面再补入修改App后的测试结果; 由于是用有道记录的,有图片,不能复制过来,就用PDF附件上传了; 附件是测试记录:342729 ...
viphotman 意法半导体-低功耗射频
攒分,请无视
只为攒分...
gglu 嵌入式系统
【LSM6DSOX的MLC机器学习理解】--机器学习简介
本帖最后由 justd0 于 2020-5-2 12:43 编辑 LSM6DSOX机器学习模块是个挺复杂的部分,通过几天的研究,终于弄明白了基本的用法。这篇帖子将简单介绍下LSM6DSOX机器学习模块的特点和基本操作流 ......
justd0 ST MEMS传感器创意设计大赛专区
关于2.4G无线模块|UART串口转数传收发问题
我的问题是:关于2.4G无线模块的收发问题。 问题描述:我有三个数据采集需要,每个采集端我配了一个无线串口发送模块(附图),把UART串口数据转换成2.4G信号发送,但是我接收端也需要用同等型 ......
xueyongchao8805 无线连接

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1696  2892  273  1737  1631  16  11  53  8  32 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved