Q2S30 Series – 30A Quarter-Brick DC/DC Converter
48, 24V Input
3.3V, 2.5V, 2.0V, 1.8V, 1.5V Output
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Applications
•
•
•
•
Distributed power architectures
Telecommunications equipment
LAN/WAN applications
Data processing applications
Low profile (8.5mm)
1500 VDC input-to-output isolation meets
basic insulation
High efficiency - to 90% at full load
Start-up into high capacitive load
Low conducted and radiated EMI
Output overcurrent protection
Output overvoltage protection
Overtemperature protection
Back drive protection
Remote sense
Set point accuracy
±
1%
Remote on/off (primary referenced),
positive or negative logic
Output voltage trim adjust, positive or
negative
UL 1950 Recognized, CSA 22.2 No. 950-
95 certified, TUV IEC950
Description
The new Q2S30 Series of single-output DC/DC converters offer unprecedented density and performance in
an industry-standard, quarter-brick footprint. Patent pending technology combined with state-of-the-art
packaging techniques allows the Q2S30 to provide 30A of output current in an 8.5mm package without a
heatsink. The 100% surface mount design provides consistent high quality and reliability, and the SMT
mounting option eliminates the need for separate (additional manual) operations to mount the converters to
the motherboards during mass production.
Model
Q2S30ZA
Q2S30ZB
Q2S30ZC
Q2S30ZD
Q2S30ZE
Q2S30YA
Q2S30YB
Q2S30YC
Q2S30YD
Q2S30YE
Input
voltage
range,
VDC
36-75
36-75
36-75
36-75
36-75
18-36
18-36
18-36
18-36
18-36
Input
current,
max,
ADC
1.5
1.7
1.9
2.3
3.1
3.1
3.6
4.0
4.9
6.3
Selection Chart
Output
Output rated
voltage,
current,
I rated
VDC
ADC
1.5
30
1.8
30
2.0
30
2.5
30
3.3
30
1.5
30
1.8
30
2.0
30
2.5
30
3.3
30
Output
Ripple /
Noise, Typ,
mV p-p
30
30
30
30
30
30
30
30
30
30
Efficiency
@ I rated,
Typical,
%
83
85
85
87
88
82
83.5
84.5
86
88
REV. JUN 17, 2002
Page 1 of 11
Q2S30 Series – 30A Quarter-Brick DC/DC Converter
48, 24V Input
3.3V, 2.5V, 2.0V, 1.8V, 1.5V Output
Absolute Maximum Ratings
Data Sheet
Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely effect
long-term reliability, and cause permanent damage to the converter.
Parameter
Input voltage
Operating Temperature
Storage Temperature
ON/OFF Control Voltage
Conditions/Description
Continuous
Per GR-513, tp = 10µs
At 100% load
Referenced to -Vin
Min
Max
75
100
100
125
20
Units
VDC
VDC
°C
°C
VDC
-40
-40
Environmental and Mechanical Specifications
All specifications apply over specified input voltage, output load, and temperature range, unless otherwise
noted.
Parameter
Shock
Sinusoidal Vibration
Weight
Water Washing
MTBF
Conditions/Description
Halfsine wave, 3 axes
GR-63-Core, Section 5.A.2
Standard process
Telcordia TR-332, Method I Case 1
Min
50
1
Nom
Max
Units
g
Oz/g
MHrs
102(28)
Yes
2.6
Isolation Specifications
All specifications apply over specified input voltage, output load, and temperature range, unless otherwise
noted.
Parameter
Insulation Safety Rating
Isolation Voltage
Isolation Resistance
Isolation Capacitance
Conditions/Description
Min
1500
10
230
Nom
Basic
Max
Units
VDC
MΩ
pF
Input Specifications
All specifications apply over specified input voltage, output load, and temperature range, unless otherwise
noted.
Parameter
Input Voltage
Turn-On Input Voltage
Turn-Off Input Voltage
Turn-On Time
Input Reflected Ripple Current
Inrush Transient
REV. JUN 17, 2002
Conditions/Description
Continuous
Ramping Up Vin= 36-75
Vin = 18-36
Ramping Down Vin = 36-75
Vin = 18-36
To Output Regulation Band
100% Resistive Load
25 MHz Bandwidth
Vin = Vin max
Min
36
18
33
16
31
15
Nom
48
24
Max
75
36
35
17.5
33
16.5
Units
VDC
VDC
VDC
ms
10
0.1
mA
pk.pk
A
2
s
2.5
Page 2 of 11
Q2S30 Series – 30A Quarter-Brick DC/DC Converter
48, 24V Input
3.3V, 2.5V, 2.0V, 1.8V, 1.5V Output
Output Specifications
Data Sheet
All specifications apply over specified input voltage, output load and temperature range, unless otherwise
noted.
Parameter
Output Voltage Setpoint Accuracy
Output Current*
Line Regulation
Load Regulation
Total Output Voltage Regulation
Remote Sense Headroom***
Dynamic Regulation
Peak Deviation
Settling Time
Admissible Load Capacitance
Output Current Limit Threshold**
Switching Frequency
Over voltage Protection,
Non Latching
Trim Range
Conditions/Description
Vin=Vin.nom, Full Load
Vin min to Vin max,
Iout max
Vin=Vnom, Iout min to
Iout max
Over all input voltage, load,
and temperature conditions
50-75% load step change
di/dt = 5 A/μs
to 1% error band
Iout max, Nom Vin
Vout
≤0.97Vout
nom
Over all input voltage and
load conditions
Iout max, Vin=Vnom
Min
-1
0
Nom
Max
1
30
±5
±5
3
10%
160
100
33
115
-20
36
435
122
30,000
40
127
+10
Units
%Vout
ADC
mV
mV
%Vout
%Vout
mV
µs
µF
ADC
kHz
%Vout
%Vout
±2
±2
-3
** Overcurrent protection is non-latching with auto recovery.
*** Vout can be increased up to 10% via the sense leads or up to 10% via the trim function, however total
output voltage trim from all sources should not exceed 10% of Vout (NOM) in order to ensure specified
operation of over-voltage protection circuitry.
Feature Specifications
All specifications apply over specified input voltage, output load, and temperature range, unless otherwise
noted.
Parameter
Shutdown (ON/OFF)
Negative Logic
- Converter ON
- Converter OFF
Positive Logic
- Converter ON
- Converter OFF
Overtemperature
Protection
Conditions/Description
On/Off signal is low – converter is ON
Low logic range
High logic range
On/Off signal is low –converter is OFF
High logic range
Low logic range
Shut down
Min
Nom
Max
Units
-20
2.4
2.4
-20
118
0.8
20
20
0.8
VDC
VDC
VDC
VDC
°C
REV. JUN 17, 2002
Page 3 of 11
Q2S30 Series – 30A Quarter-Brick DC/DC Converter
48, 24V Input
3.3V, 2.5V, 2.0V, 1.8V, 1.5V Output
Characteristic curves
0.95
0.95
Data Sheet
0.90
0.90
0.85
Efficiency
0.85
0.80
0.75
0.70
72 V
54 V
36 V
Efficiency
0.80
0.75
0.70
72 V
54 V
36 V
0.65
0
5
10
15
20
25
30
35
0.65
0
5
10
15
20
25
30
35
Load Current [Adc]
Load Current [Adc]
Fig .1
Q2S30ZE (3.3V) Efficiency vs. Load
0.95
0.90
0.85
Efficiency
0.80
0.75
0.70
0.65
0
5
10
15
20
25
30
35
Load Current [Adc]
72 V
54 V
36 V
Fig. 4
Q2S30ZB (1.8V) Efficiency vs. Load
0.95
0.90
0.85
Efficiency
0.80
0.75
0.70
0.65
0
5
10
15
20
25
30
35
Load Current [Adc]
72 V
54 V
36 V
Fig. 2
Q2S30ZD (2.5V) Efficiency vs. Load
0.95
0.90
0.85
Efficiency
Fig. 5
Q2S30ZA (1.5V) Efficiency vs. Load
0.95
0.90
0.85
Efficiency
0.80
0.75
0.70
0.65
36 V
27 V
18 V
0.80
0.75
0.70
0.65
0
5
10
15
20
25
30
35
Load Current [Adc]
72 V
54 V
36 V
0
5
10
15
20
25
30
35
Load Current [Adc]
Fig. 3
Q2S30ZC (2.0V) Efficiency vs. Load
Fig. 6
Q2S30YE (3.3V) Efficiency vs. Load
REV. JUN 17, 2002
Page 4 of 11
Q2S30 Series – 30A Quarter-Brick DC/DC Converter
48, 24V Input
3.3V, 2.5V, 2.0V, 1.8V, 1.5V Output
0.95
0.90
0.85
Efficiency
Efficiency
0.80
0.75
0.70
0.65
0
5
10
15
20
25
30
35
Load Current [Adc]
36 V
27 V
18 V
Data Sheet
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0
5
10
15
20
25
30
35
Load Current [Adc]
36 V
27 V
18 V
Fig. 7
Q2S30YD (2.5V) Efficiency vs. Load
0.95
0.90
0.85
Efficiency
0.80
0.75
0.70
0.65
0
5
10
15
20
25
30
35
Load Current [Adc]
36 V
27 V
18 V
Fig. 10
Q2S30YA (1.5V) Efficiency vs. Load
Typical Application
Fig. 11 shows the recommended connections for
the Q2S30 Series converter.
Fig. 11
Typical Application of Q2S30 Series
Fig. 8
Q2S30YC (2.0V) Efficiency vs. Load
0.95
0.90
0.85
Efficiency
0.80
0.75
0.70
0.65
0
5
10
15
20
25
30
35
Load Current [Adc]
36 V
27 V
18 V
The Q2S30 Series converters do not require any
external components for proper operation.
However, if the distribution of the input voltage to
the converter contains significant inductance, an
input capacitor may be required to enhance
performance of the converter. A minimum of a
100µF electrolytic capacitor with the ESR<0.7Ω is
recommended for the Q2S30 series.
If magnitude of the inrush current needs to be
limited, see the “Inrush Current Control
Application Note” on the Power-One website at
www.power-one.com.
For output decoupling we recommend using 10μF
tantalum and 1μF ceramic capacitors connected
directly across the output pins of the converter.
Note that the capacitors do not substitute the
filtering required by the load.
Fig. 9
Q2S30YB (1.8V) Efficiency vs. Load
REV. JUN 17, 2002
Page 5 of 11
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
