HD66503
(240-Channel Common Driver with Internal LCD
Timing Circuit)
ADE-207-301(Z)
'99.9
Rev. 0.0
Description
The HD66503 is a common driver for liquid crystal dot-matrix graphic display systems. This device
incorporates a 240 liquid crystal driver and an oscillator, and generates timing signals (alternating signals
and frame synchronizing signals) required for the liquid crystal display. It also achieves low current
consumption of 100
µA
through the CMOS process. Combined with the HD66520, a 160-channel column
driver with an internal RAM, the HD66503 is optimal for use in displays for portable information tools.
Features
•
LCD timing generator: 1/120, 1/240 duty cycle internal generator
•
•
•
•
•
•
•
•
•
•
•
Alternating signal waveform generator: Pin programmable 2 to 63 line inversion
Recommended display duty cycle: 1/120, 1/240 (master mode): 1/120 to 1/240 (slave mode)
Number of LCD driver: 240
Power supply voltage: 2.7 to 5.5V
High voltage: 8 to 28-V LCD drive voltage
Low power consumption: 100
µA
(during display)
Internal display off function
Oscillator circuit with standby function: 130 kHz (max)
Display timing operation clock: 65 kHz (max) (operating at 1/2 system clock)
Package: 272-pin TCP
CMOS process
Ordering Information
Type No.
HD66503TA0
HD66503TB0
TCP
Straight TCP
Folding TCP
Outer Lead Pitch (µm)
200
200
1
HD66503
Pin Arrangement
X240
X239
X238
X237
X236
X235
X234
X233
X232
X231
1
2
3
4
5
6
7
8
9
10
272
271
270
269
268
267
266
265
264
263
262
261
260
259
258
V2R
V5R
V6R
V1R
V
EER
V
CC2
M/S
DOC
FLM
CL1
M
RESET
DISPOFF
DUTY
MEOR
Top View
257
256
255
254
253
252
251
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
231
232
233
234
235
236
237
238
239
240
250
249
248
247
246
245
244
243
242
241
MWS0
MWS1
MWS2
MWS3
MWS4
MWS5
SHL
GND
C
R
CR
V
CC1
V
EEL
V1L
V6L
V5L
V2L
Note : This figure does not specify the tape carrier package dimensions.
2
HD66503
Pin Description
Classi-
fication
Power
supply
Symbol
V
CC1
,
V
CC2
GND
V
EEL
,
V
EER
V1L, R
V2L, R
V5L, R
V6L, R
Control
signals
M/S
Pin No.
246
267
250
245
268
244
269
241
272
242
271
243
270
266
Pin Name
V
CC
GND
V
EE
V1
V2
V5
V6
I/O
Power
supply
Power
supply
Power
supply
Input
Input
Input
Input
Number
of Pins Functions
2
1
2
2
2
2
2
1
Controls the initiation and termination of
the LCD timing generator. In addition,
the input/output is determined of 4
signal pins: display data transfer clock
(CL1); first line marker (FLM);
alternating signal (M); and display off
control (DOC). See Table 1 for details.
Selects the display duty cycle.
Low level: 1/120 display duty ratio
High level: 1/240 display duty ratio
The number of line in the line
alternating waveform is set during
master mode.
The number of lines can be set
between 10 and 63.
When using the external alternating
signal or during slave mode, set the
number of lines to 0. See Table 2.
During master mode, the signals
alternating waveform output from pin M
is selected.
During low level, the line alternating
waveform is output from pin M.
During high level, pin M outputs an
EOR (exclusive OR) waveform between
a line alternating waveform and frame
alternating waveform. Set the pin to low
during slave mode. See Table 3.
V
CC
–V
EE
: LCD drive circuits power
supply
LCD drive level power supply
See Figure 1.
V
CC
–GND: logic power supply
Master/slave Input
DUTY
259
Duty
Input
1
MWS0 to
MWS5
257
256
255
254
253
252
MWS0
MWS1
MWS2
MWS3
MWS4
MWS5
Input
6
MEOR
258
M Exclusive- Input
OR
1
3
HD66503
Classi-
fication
Control
signals
Symbol
CR, R, C
Pin No.
247
248
249
261
Pin Name
CR
R
C
Reset
Input
I/O
Number
of Pins Functions
3
These pins are used as shown in Figure
4 in master mode, and as shown in
Figure 5 in slave mode.
The following initiation will be proceeded
by setting to initiation.
1) Stops the internal oscillator or the
external oscillator clock input.
2) Initializes the counters of the liquid
crystal display timing generator and
alternating signal (M) generator.
3) Set display off control output (DOC)
to low and turns off display.
After reset, display off control output
(DOC) will stay low for four more frame
cycles (four clocks of FLM signals) to
prevent error display at initiation. The
electrical characteristics are shown in
Table 4. See Figure 2.
However, when reset is performed
during operation, RAM data in the
HD66520 which is used together with
the HD66503 may be destroyed.
Therefore, write data to the RAM again.
The bidirectional shift register shifts data
at the falling edge of CL1. During master
mode, this pin-outputs a data transfer
clock with a two times larger cycle than
the internal oscillator (or the cycle of the
external clock) with a duty of 50%.
During slave mode, this pin inputs the
external data transfer clock.
During master mode, pin FLM outputs
the first line marker. During slave mode,
this pin inputs the external data first line
marker. The shift direction of the first
line marker is determined by DUTY and
SHL signal as follows. Set signal DUTY
to high during slave mode. See Table 5.
Pin M inputs and outputs the alternating
signal of the LCD output.
RESET
1
LCD
timing
CL1
263
Clock 1
I/O
1
FLM
264
First line
marker
I/O
1
M
262
M
I/O
1
4
HD66503
Classi-
fication
LCD
timing
Symbol
SHL
Pin No.
251
Pin Name
Shift left
I/O
Input
Number
of Pins Functions
1
Pin SHL switches the shift direction of
the shift register. Refer to FLM for
details.
Turns off the LCD.
During master mode, liquid crystal drive
output X1 to X240 can be set to level V1
by setting the pin to low. By setting the
HD66520 to level V1 in the same way,
the data on the display can be erased.
During slave mode, set
DISPOFF
high.
Controls the display-off function. During
master mode, pin
DOC
becomes an
output pin and controls display off after
reset and display off according to signal
DISPOFF.
In this case, connect this
signal to the HD66520’s pin
DISPOFF.
During slave mode, pin
DOC
becomes
an input pin for display off control signal.
In this case, connect this signal to the
master HD66503’s pin
DOC.
Selects one from among four levels (V1,
V2, V5, and V6) depending on the
combination of M signal and display
data. See Figure 3.
DISPOFF
260
Display off
Input
1
DOC
265
Display off
control
I/O
1
LCD
drive
output
X1 to
X240
240
to 1
X1 to
X240
Output 240
Note: 30 input/outputs (excluding driver block)
5
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