D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
FM3570 CPU CONFIGURATION CONTROLLER
Register/Multiplexer for Microprocessor VID
Preliminary
March 2001
FM3570
CPU CONFIGURATION CONTROLLER
Register/Multiplexer for Microprocessor VID
General Description
The Fairchild FM3570 replaces the CPU motherboard’s configu-
ration switches with an electronic implementation consisting of a
4/5-bit multiplexed, 1-bit latched port, standard 2-wire bus inter-
face, and non-volatile latches.
The FM3570 multiplexes the I-port input signals with two internal
non-volatile registers that can be loaded through the serial port.
The multiplexer is selected via the serial port and defaults to the
I-port upon power-up. Pull-up resistors are provided on the input
port to accommodate connections to open-drain outputs and to
eliminate the need for external resistors. The device has open-
drain outputs for easy interface to devices with different V
DD
levels.
The serial port is an IIC compatible slave-only interface and
supports both 100kbit and 400kbit modes of operation. The port
is used to read the I-Port, write data to the internal non-volatile
registers and select whether the I-port or one of the internal non-
volatile registers is output to the Y-port. The FM3570 is fabricated
with advanced CMOS technology to achieve high density and low
power operation.
Features
I
Extended Operating Voltage Range 3.0V-5.5V
I
IIC Compatible Slave Interface.
I
ESD performance: Human body model > 2000V
I
Choice of 2.5V Outputs or Open-Drain Outputs
Block Diagram
Non_Mux_Out
I[4:0]
Y[4:0]
Mux1
SOPRA
Mux2
SOPRB
MXSB, MXSA
IIC Read Logic
Mux3
Control Logic
MUXSEL
OVRD
SDA
SCL
IIC
Interface
Shift
Register
Slave Address
Register
ASEL
Comparator
Start/Stop
Logic
© 2001 Fairchild Semiconductor Corporation
FM3570 Rev. A
1
www.fairchildsemi.com
FM3570 CPU CONFIGURATION CONTROLLER
Register/Multiplexer for Microprocessor VID
Ordering Code
FM
3570
XXXX
X
Blank
X
Tube
Tape & Reel
M20
MT20
20-Pin SO Package Option
20-Pin TSSOP Package Option
Order Number
FM3570MT20
FM3570MT20X
FM3570M20
FM3570M20X
Package Number
MTC20
MTC20
M20B
M20B
Package Description
20-Pin TSSOP
20-Pin TSSOP T & R
20 Pin SO
20 Pin SO T & R
For all other combinations, check with Fairchild Marketing/Sales
Pin Connection Diagram
20-Pin Packages
FM3570
SCL
SDA
OVRD
I0
I1
I2
I3
I4
Level
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
ASEL
WP
Non_Mux_Out
MUXSEL
Y0
Y1
Y2
Y3
Y4
Pin Description
Pin Name
I [0:4]
Y [0:4]
SCL
OVRD
WP
Non_mux_out
MUXSEL
EPV
ASEL
SDA
Description
Data Inputs w/Pullups (10K-40K)
Open-Drain Data Outputs
Serial Port Clock Input (120K pullup)
Override Input. Sets all outputs to 0
Write Protect Input
Non-Multiplexed Output
Multiplexer Select Input
I Port Pull-up Resistor Voltage
Address Select Input
Serial Port Data I/O (120K pull-up)
2
FM3570 Rev. A
www.fairchildsemi.com
FM3570 CPU CONFIGURATION CONTROLLER
Register/Multiplexer for Microprocessor VID
Functional Description
The FM3570 block diagram is shown in Figure 1. The device has
two primary functional modes of operationi and an additional
mode for programming the device.
Serial Output Port Register A(SOPRA) Address: 00H
- A read/
write register that contains the new value to be written to output
Port-Y and the multiplexer select bit.
Serial Output Port Register B(SOPRB) Address: 01H
- A read/
write register that contains the new value to be written to output
Port-Y and the multiplexer select bit.
Parallel Input Port Register (PIPR) Address: 02H
- A read-only
register that is loaded with the 5-bit value of the I-Port.
Operational Modes
During standard operation, the device will either pass an address
to the Y-Port from the I-Port or from an internally programmed
value.
The I-port values are generated from the motherboard of the
system and may be hardwired or driven by another device. Pull-
up resistors are provided on the device to accommodate this
device being driven by open-drain output drivers. The voltage
level to which the I-port is pulled up to is determined by the voltage
on the EPV pin. The device expects standard CMOS input signals.
The the non-multiplexed output is always at CMOS levels. The
OVRD (override) input, when set to 0, will cause all the outputs to
be set to 0. The WP signal, if set to logic 1, will prevent data from
being written to the non-volatile register.
The MUXSEL input, when set to logic 0, will select the data from
the non-volatile register to drive on the Y0-4 outputs. if set to logic
1, the data from the inputs are selected instead. the non_mux_out
latch is transparent when the MUXSEL signal is at logic 0, and will
latch when the MUXSEL is in a logic 1 state.
Serial Output Port Register (SOPR)
(Address 000b and 001b)
MXSB MXSA
0
b7
0
b6
I5
b5
NMO
b4
Data Field
I3
b3
I2
b2
I1
b1
I0
b0
b7-b6 - Multiplexer Select Bits (MXSB, MXSA)
00 - Multiplexer passes the SOPR(A).
01 - Multiplexer passer the SOPR(B).
10 - Multiplexer defaults to passing the I-Port Value.
b5, b3-b0 - Data Field. New value to be output through the
multiplexer.
NMO - Non-multiplexed output from internal non-volatile bit.
Output Port: Y0-Y4
The output port is an open-drain output to allow for easy connec-
tion to devices running at different voltage levels. The port is
always active and either passes the value on the I-Port or the value
in the Serial output port (SOPR). Changing the Mux Path is
accomplished by writing to b7 of the Serial Input Port Register.
SOPR-b7 defaults to a value of zero at power up and the default
path is from the I-port though to the output port. The multiplexer
only updates when an IIC stop condition is observed.
Parallel Input Port Register (PIPR)
(Address 002b)
Address Field
0
b7
0
b6
0
b5
I4
b4
Data Field
I3
b3
I2
b2
I1
B1
I0
b0
b7-b5 - Address field. Value is always 000
b4-b0 - Data Field. Value is equal to the value on the I-Port.
The external Port Register captures the value on the I-Port. Data
is latched into this register on the first clock after a start condition
is seen. This insures that a valid value will always be in this register
if it is read. This register is a-read only register with respect to the
IIC port.
Register Description
The FM3570 has 3 registers in total. These registers are made up
of a combination of read-only, write-only and read/write bits. The
two registers are listed below.
3
FM3570 Rev. A
www.fairchildsemi.com
FM3570 CPU CONFIGURATION CONTROLLER
Register/Multiplexer for Microprocessor VID
OVRD
0
0
MUXSEL
0
1
MXSB
X
X
MXSA
X
X
Mux_
outputs
all 0’s
Mux_
inputs
Mux_
inputs
1
0
1
0
1
0
0
0
1
1
0
0
1
0
1
1
1
1
Note 2
Note 1
From
Non-
volatile
register
(SOPRA)
Do not use this
c ombination
From
From No n-
Non-
volatile
volatile
register
register
(SOPRB)
(SOPRB)
Mux_i
From No n-
nputs
volatile
register
(SOPRA or
SOPRB)
No n_mux_
ouput
all 0’s
latched
NMO
(see Note 1)
latched
NMO
(see Note 1)
From No n-
volatile
register
(SOPRA)
The IIC protocol uniquely defines START and STOP conditions.
A START condition is defined as a HIGH to LOW transition of the
SDA signal while SCL is HIGH. A STOP condition is defined as a
LOW to HIGH transition of the SDA signal while SCL is HIGH.
These are shown in Figure 2.
Device Addressing
The device uses 7-bit IIC addressing.The address has been
defined as 1001 110 if the ASEL input is ‘1’ and 0110 111 if the
ASEL input is ‘0’. The address byte is the first byte of data sent after
a start condition. This is the only address that this device will
respond to. The device will not respond to the general call address
0000 000.
Reading from the Registers
Data can be read from both of the internal registers. All reads are non-
destructive and do not change the value in the register or the internal
state of the device. When a start condition is received with a read
request, both registers can be read out in the following sequence:
(1)
(2)
(3)
SOPRA: Serial Output Port Register A
SPORB: Serial Output Port Register B
PIPR: PORT-I Value
Note 1:
Latched NMO state will be the value present on the NMO output at the time
of the MUXSEL input transitioning from logic 0 to logic 1 state.
Note 2:
Output depends on previously selected state of MXSB and MXSA bits
written to device.
If so desired, only the SOPRA register can be read. This is
accomplished by issuing a stop command after the acknowledge
bit for the first byte is read. If no stop is issued, the device will output
the registers in the above sequence.
Multiplexer Logic
The output multiplexer logic determines what value is actually
output to the Y-port. The value that it output is dependent upon
b7-b6 of the SOPRA and SOPRB registers, as well as the
external MUXSEL and OVRD inputs. There is only one set of
MXS bits in the SOPRA and SOPRB registers. Regardless of
whether one writes to SPRA or SOPRB register for setting the
MXS bits, the result is the same. These same bits appear in
both the registers. If the MUXSEL is logic 0 and OVRD is logic
1, then, if b7, b6 is “10” then the value on the I-port is passed.
when b7 is “00” the value of the SOPRA register is passed on
the next IIC stop condition, and when b7 is “01” the value of the
SOPRB register is passed on the next IIC stop condition. If
MUXSEL is logic 1 and OVRD is logic 1, the input lines I0-4 are
used to drive the outputs. The above table describes all the
combinations.
Writing to the Registers
Data is written to the SOPR registers through the serial port
interface. When a write request is received with the Start Address
it is assumed that the intent is to write to the SOPR registers. The
value placed in the least 6 significant bits of the register contain the
new code to be placed in the SOPR A/B registers. The value of the
two most significant bits must contain the address of the destina-
tion register SOPRA or SOPRB.
The internal non-volatile latch takes about 10 ms to update its data.
The new data is reflected on the outputs after the internal non-volatile
latch is updated, if the corresponding select bits (MXSx, OVRD and
MUXSEL) are set to reflect the state of the non-volatile register.
Register Read Sequence
S
S
IIC Interface
The IIC Interface is a standard slave interface. As a slave interface
the device will not generate its own clock. Data can be read from
and written into the device. Commands for reading and writing the
registers are generated by the IIC Master.
Slave
Address
1001110
SOPRA
R A Register
1
SOPRB
A Register
PIPR
A Register
A P
A 00bbbbbb A 00bbbbbb A 00bbbbbb A P
Register Write Sequence
S
S
START and STOP Conditions
SDA
Slave
SOPRx
Address W A Register
1001110
0
A xxbbbbbb
A S
A S
xx = Register Selection bits (MXSB and MXSA) xx = 00 selects SOPRA, 01
selects SOPRB
SCL
START
Condition
STOP
Condition
Register Write Sequence using
Repeated Start Condition
Slave
SOPRA
Slave
SOPRx
S Address R A Register A S Address W A Register A P
S 1001110 1 A 00bbbbbb A S 1001110 0
A xxbbbbbb A P
Figure 2. START & STOP Conditions
Figure 4
4
FM3570 Rev. A
www.fairchildsemi.com
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
