OMC 942723026
H8/3042 Series
H8/3042, H8/3041, H8/3040
Hardware Manual
ADE-602-067
Preface
The H8/3042 Series is a series of high-performance microcontrollers that integrate system
supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory
access controller (DMAC), a refresh controller, and other facilities.
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory.
Seven operating modes (modes 1 to 7) are provided, offering a choice of initial data bus width and
address space size.
With these features, the H8/3042 Series can be used to implement compact, high-performance
systems easily.
This manual describes the hardware of the H8/3042 Series. For details of the instruction set, refer
to the H8/300H Programming Manual.
Contents
Section 1
1.1
1.2
1.3
Overview
.....................................................................................................
1.4
Overview.........................................................................................................................
Block Diagram................................................................................................................
Pin Description ...............................................................................................................
1.3.1
Pin Arrangement.............................................................................................
1.3.2
Pin Functions ..................................................................................................
Pin Functions ..................................................................................................................
1
1
5
6
6
7
10
Section 2
2.1
CPU
............................................................................................................... 15
15
15
16
17
18
19
19
20
21
22
23
23
24
26
26
27
28
38
39
39
39
42
46
46
47
47
49
50
50
50
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Overview.........................................................................................................................
2.1.1
Features...........................................................................................................
2.1.2
Differences from H8/300 CPU .......................................................................
CPU Operating Modes....................................................................................................
Address Space.................................................................................................................
Register Configuration....................................................................................................
2.4.1
Overview.........................................................................................................
2.4.2
General Registers............................................................................................
2.4.3
Control Registers ............................................................................................
2.4.4
Initial CPU Register Values ............................................................................
Data Formats...................................................................................................................
2.5.1
General Register Data Formats.......................................................................
2.5.2
Memory Data Formats....................................................................................
Instruction Set.................................................................................................................
2.6.1
Instruction Set Overview ................................................................................
2.6.2
Instructions and Addressing Modes................................................................
2.6.3
Tables of Instructions Classified by Function ................................................
2.6.4
Basic Instruction Formats ...............................................................................
2.6.5
Notes on Use of Bit Manipulation Instructions ..............................................
Addressing Modes and Effective Address Calculation ..................................................
2.7.1
Addressing Modes ..........................................................................................
2.7.2
Effective Address Calculation ........................................................................
Processing States ............................................................................................................
2.8.1
Overview.........................................................................................................
2.8.2
Program Execution State ................................................................................
2.8.3
Exception-Handling State...............................................................................
2.8.4
Exception-Handling Sequences ......................................................................
2.8.5
Bus-Released State .........................................................................................
2.8.6
Reset State ......................................................................................................
2.8.7
Power-Down State ..........................................................................................
2.9
Basic Operational Timing...............................................................................................
2.9.1
Overview.........................................................................................................
2.9.2
On-Chip Memory Access Timing...................................................................
2.9.3
On-Chip Supporting Module Access Timing .................................................
2.9.4
Access to External Address Space..................................................................
51
51
51
53
54
Section 3
3.1
MCU Operating Modes
........................................................................... 55
55
55
56
57
58
60
60
60
60
60
60
60
61
61
3.2
3.3
3.4
3.5
3.6
Overview.........................................................................................................................
3.1.1
Operating Mode Selection ..............................................................................
3.1.2
Register Configuration....................................................................................
Mode Control Register (MDCR) ....................................................................................
System Control Register (SYSCR).................................................................................
Operating Mode Descriptions.........................................................................................
3.4.1
Mode 1 ............................................................................................................
3.4.2
Mode 2 ............................................................................................................
3.4.3
Mode 3 ............................................................................................................
3.4.4
Mode 4 ............................................................................................................
3.4.5
Mode 5 ............................................................................................................
3.4.6
Modes 6 and 7.................................................................................................
Pin Functions in Each Operating Mode..........................................................................
Memory Map in Each Operating Mode..........................................................................
Section 4
4.1
Exception Handling
.................................................................................. 69
69
69
69
70
71
71
71
74
75
76
77
78
4.2
4.3
4.4
4.5
4.6
Overview.........................................................................................................................
4.1.1
Exception Handling Types and Priority..........................................................
4.1.2
Exception Handling Operation .......................................................................
4.1.3
Exception Vector Table...................................................................................
Reset ...............................................................................................................................
4.2.1
Overview.........................................................................................................
4.2.2
Reset Sequence ...............................................................................................
4.2.3
Interrupts after Reset.......................................................................................
Interrupts.........................................................................................................................
Trap Instruction...............................................................................................................
Stack Status after Exception Handling ...........................................................................
Notes on Stack Usage .....................................................................................................
Section 5
5.1
Interrupt Controller
................................................................................... 79
79
79
80
81
Overview.........................................................................................................................
5.1.1
Features...........................................................................................................
5.1.2
Block Diagram................................................................................................
5.1.3
Pin Configuration............................................................................................
5.2
5.3
5.4
5.5
5.1.4
Register Configuration.................................................................................... 81
Register Descriptions...................................................................................................... 82
5.2.1
System Control Register (SYSCR)................................................................. 82
5.2.2
Interrupt Priority Registers A and B (IPRA, IPRB) ....................................... 83
5.2.3
IRQ Status Register (ISR) .............................................................................. 90
5.2.4
IRQ Enable Register (IER)............................................................................. 91
5.2.5
IRQ Sense Control Register (ISCR) ............................................................... 92
Interrupt Sources............................................................................................................. 93
5.3.1
External Interrupts .......................................................................................... 93
5.3.2
Internal Interrupts ........................................................................................... 94
5.3.3
Interrupt Vector Table ..................................................................................... 94
Interrupt Operation ......................................................................................................... 98
5.4.1
Interrupt Handling Process ............................................................................. 98
5.4.2
Interrupt Sequence .......................................................................................... 103
5.4.3
Interrupt Response Time................................................................................. 104
Usage Notes .................................................................................................................... 105
5.5.1
Contention between Interrupt and Interrupt-Disabling Instruction ................ 105
5.5.2
Instructions that Inhibit Interrupts .................................................................. 106
5.5.3
Interrupts during EEPMOV Instruction Execution ........................................ 106
Section 6
6.1
Bus Controller
............................................................................................ 107
6.2
6.3
6.4
Overview......................................................................................................................... 107
6.1.1
Features........................................................................................................... 107
6.1.2
Block Diagram................................................................................................ 108
6.1.3
Input/Output Pins............................................................................................ 109
6.1.4
Register Configuration.................................................................................... 109
Register Descriptions...................................................................................................... 110
6.2.1
Bus Width Control Register (ABWCR) ......................................................... 110
6.2.2
Access State Control Register (ASTCR)........................................................ 111
6.2.3
Wait Control Register (WCR)......................................................................... 112
6.2.4
Wait State Control Enable Register (WCER) ................................................. 113
6.2.5
Bus Release Control Register (BRCR)........................................................... 114
Operation ........................................................................................................................ 116
6.3.1
Area Division.................................................................................................. 116
6.3.2
Chip Select Signals ......................................................................................... 118
6.3.3
Data Bus.......................................................................................................... 119
6.3.4
Bus Control Signal Timing ............................................................................. 120
6.3.5
Wait Modes ..................................................................................................... 128
6.3.6
Interconnections with Memory (Example)..................................................... 134
6.3.7
Bus Arbiter Operation..................................................................................... 136
Usage Notes .................................................................................................................... 139
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