June 1997
NDS336P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
SuperSOT
TM
-3 P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low voltage
applications such as notebook computer power management,
portable electronics, and other battery powered circuits where
fast high-side switching, and low in-line power loss are needed
in a very small outline surface mount package.
Features
-1.2 A, -20 V, R
DS(ON)
= 0.27
Ω
@ V
GS
= -2.7 V
R
DS(ON)
= 0.2
Ω
@ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.0V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface
package.
Mount
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
Parameter
Drain-Source Voltage
T
A
= 25°C unless otherwise noted
NDS336P
-20
±8
(Note 1a)
Units
V
V
A
Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
-1.2
-10
0.5
0.46
-55 to 150
W
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
250
75
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS336P Rev. E
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSS
I
GSS
V
GS(th)
R
DS(ON)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= -250 µA
V
DS
= -16 V, V
GS
= 0 V
T
J
=55°C
Gate - Body Leakage Current
Gate - Body Leakage Current
V
GS
= 8 V, V
DS
= 0 V
V
GS
= -8 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= -250 µA
T
J
=125°C
Static Drain-Source On-Resistance
V
GS
= -2.7 V, I
D
= -1.2 A
T
J
=125°C
V
GS
= -4.5 V, I
D
= -1.3 A
I
D(ON)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
Forward Transconductance
V
GS
= -2.7 V, V
DS
= -5 V
V
DS
= -5 V, I
D
= -1.2 A
V
DS
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
-2
-3
-0.5
-0.3
-0.78
-0.58
0.22
0.34
0.16
-20
-1
-10
100
-100
V
µA
µA
nA
nA
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
-1
-0.8
0.27
0.49
0.2
A
S
V
Ω
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
360
170
60
pF
pF
pF
SWITCHING CHARACTERISTICS
(Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= -10 V, I
D
= -1.2 A,
V
GS
= -4.5 V
V
DD
= -5 V, I
D
= -1 A,
V
GS
= -4.5 V, R
GEN
= 6
Ω
8
29
33
23
5.7
0.7
1.8
15
50
60
45
8.5
ns
ns
ns
ns
nC
nC
nC
NDS336P Rev. E
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
Maximum Continuous Source Current
Maximum Pulsed Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -0.42
(Note 2)
-0.65
-0.42
-10
-1.2
A
A
V
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solde mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
P
D
(
t
) =
T
J
−T
A
R
θJA
(t)
=
T
J
−T
A
R
θJC
+R
θCA
(t)
=
I
2
(
t
) ×
R
DS(ON)@T
J
D
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250
o
C/W when mounted on a 0.02 in
2
pad of 2oz copper.
b. 270
o
C/W when mounted on a 0.001 in
2
pad of 2oz copper.
1a
1b
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS336P Rev. E
Typical Electrical Characteristics
-10
I
D
, DRAIN-SOURCE CURRENT (A)
2
GS
-3.5
R
DS(on)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V
= -4.5V
-4.0
1.8
1.6
-8
V
GS
=-2.0V
-2.5
-3.0
-2.7
-2.5
-6
1.4
1.2
1
0.8
0.6
-2.7
-3.0
-3.5
-4.0
-4.5
-4
-2.0
-2
0
0
-1
V
DS
-2
-3
-4
-5
0
-2
-4
-6
-8
-10
, DRAIN-SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage.
1.6
DRAIN-SOURCE ON-RESISTANCE
DRAIN-SOURCE ON-RESISTANCE
2
R
DS(ON)
, NORMALIZED
1.4
I
D
= -1.2A
V = -2.7V
GS
V
GS
= -2.7V
1.8
1.6
1.4
R
DS(on)
, NORMALIZED
TJ = 125°C
25°C
1.2
1
1.2
-55°C
1
0.8
0.6
0.8
0.6
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0
-2
-4
-6
I , DRAIN CURRENT (A)
D
-8
-10
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation
with Drain Current and Temperature.
-5
1.2
V
DS
= -5V
T = -55°C
J
GATE-SOURCE THRESHOLD VOLTAGE
-25°C
V
GS(th)
, NORMALIZED
-125°C
1.1
1
0.9
0.8
0.7
0.6
-50
-4
V
DS
= V
GS
I
D
= -250µA
I
D
, DRAIN CURRENT (A)
-3
-2
-1
0
-0.5
-1
V
GS
-1.5
-2
-2.5
-3
-25
, GATE TO SOURCE VOLTAGE (V)
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation
with Temperature.
NDS336P Rev. D
Typical Electrical Characteristics
(continued)
1.06
5
D
DRAIN-SOURCE BREAKDOWN VOLTAGE
-I
S
, REVERSE DRAIN CURRENT (A)
I
1.04
= - 250µA
V
GS
= 0V
1
BV
DSS
, NORMALIZED
T J = 125°C
0.1
1.02
25°C
0.01
1
-55°C
0.98
0.001
0.96
-50
-25
0
T
J
25
50
75
100
125
150
0.0001
0.2
, JUNCTION TEMPERATURE (°C)
0.4
0.6
0.8
1
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 7. Breakdown Voltage Variation with
Temperature
.
Figure 8. Body Diode Forward Voltage Variation
with Source Current and
Temperature
.
800
-V
GS
, GATE-SOURCE VOLTAGE (V)
500
CAPACITANCE (pF)
5
I
D
= -1.2A
4
V
DS
= -5V
-15V
-10V
Ciss
300
200
3
Coss
2
100
60
40
0.1
f = 1 MHz
V
GS
= 0V
0.2
0.5
1
2
5
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Crss
1
0
10
20
0
2
4
Q
g
, GATE CHARGE (nC)
6
8
Figure 9. Capacitance Characteristics
.
Figure 10. Gate Charge Characteristics
.
V
DD
t
d(on)
t
on
t
off
t
r
90%
t
d(off)
90%
V
IN
D
R
L
V
OUT
V
OUT
10%
t
f
V
GS
R
GEN
10%
90%
G
DUT
S
V
IN
10%
50%
50%
PULSE WIDTH
INVERTED
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms.
NDS336P Rev. D
FPGA/CPLD
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