BUK9Y30-75B
N-channel TrenchMOS logic level FET
Rev. 04 — 10 April 2008
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Suitable for logic level gate drive
sources
Q101 compliant
Suitable for thermally demanding
environments due to 175
°C
rating
1.3 Applications
12 V, 24 V and 42 V loads
General purpose power switching
Automotive systems
Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
E
DS(AL)S
Quick reference
Parameter
drain-source voltage
drain current
total power dissipation
non-repetitive
drain-source
avalanche energy
gate-drain charge
Conditions
T
j
≥
25
°C;
T
j
≤
175
°C
V
GS
= 5 V; T
mb
= 25
°C;
see
Figure 1
and
4
T
mb
= 25
°C;
see
Figure 2
I
D
= 34 A; V
sup
≤
75 V;
R
GS
= 50
Ω;
V
GS
= 5 V;
T
j(init)
= 25
°C;
unclamped
V
GS
= 5 V; I
D
= 25 A;
V
DS
= 60 V; T
j
= 25
°C;
see
Figure 14
V
GS
= 5 V; I
D
= 15 A;
T
j
= 25
°C;
see
Figure 12
and
13
Min
-
-
-
-
Typ
-
-
-
-
Max
75
34
85
78
Unit
V
A
W
mJ
Avalanche ruggedness
Dynamic characteristics
Q
GD
-
9
-
nC
Static characteristics
R
DSon
drain-source on-state
resistance
-
25
30
mΩ
NXP Semiconductors
BUK9Y30-75B
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
Pinning
Symbol
S
S
S
G
D
Description
source
source
source
gate
mounting base;
connected to drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
1 2 3 4
SOT669 (LFPAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK9Y30-75B
LFPAK
Description
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
SOT669
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
mb
= 25
°C
t
p
≤
10
μs;
pulsed; T
mb
= 25
°C
I
D
= 34 A; V
sup
≤
75 V; R
GS
= 50
Ω;
V
GS
= 5 V;
T
j(init)
= 25
°C;
unclamped
see
Figure 3
[1][2]
[3]
Conditions
T
j
≥
25
°C;
T
j
≤
175
°C
R
GS
= 20 kΩ; T
mb
≥
25
°C;
T
mb
≤
175
°C
T
mb
= 25
°C;
V
GS
= 5 V; see
Figure 1
and
4
T
mb
= 100
°C;
V
GS
= 5 V; see
Figure 1
T
mb
= 25
°C;
t
p
≤
10
μs;
pulsed; see
Figure 4
T
mb
= 25
°C;
see
Figure 2
Min
-
-
-15
-
-
-
-
-55
-55
-
-
-
Max
75
75
15
34
24
137
85
175
175
34
137
78
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
Source-drain diode
Avalanche ruggedness
E
DS(AL)S
non-repetitive
drain-source avalanche
energy
E
DS(AL)R
repetitive drain-source
avalanche energy
[1]
[2]
[3]
-
-
J
Single-pulse avalanche rating limited by maximum junction temperature of 175
°C.
Repetitive avalanche rating limited by average junction temperature of 170
°C.
Refer to application note AN10273 for further information.
© NXP B.V. 2008. All rights reserved.
BUK9Y30-75B_4
Product data sheet
Rev. 04 — 10 April 2008
2 of 13
NXP Semiconductors
BUK9Y30-75B
N-channel TrenchMOS logic level FET
40
I
D
(A)
30
03no16
120
P
der
(%)
80
03na19
20
40
10
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
P
tot
P
tot
(25°C )
200
V
GS
5V
P
der
=
× 100 %
Fig 1. Normalized continuous drain current as a
function of mounting base temperature
10
2
I
AV
(A)
10
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
03np81
(1)
(2)
1
(3)
10
-1
10
-3
10
-2
10
-1
1 t (ms) 10
AV
(1) Single pulse;T
j
= 25
°C.
(2) Single pulse;T
j
= 150
°C.
(3) Repetitive.
Fig 3. Single-shot and repetitive avalanche rating; avalanche current as a function of avalanche period
BUK9Y30-75B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 10 April 2008
3 of 13
NXP Semiconductors
BUK9Y30-75B
N-channel TrenchMOS logic level FET
10
3
I
D
(A)
10
2
03no14
Limit R
DSon
= V
DS
/ I
D
t
p
= 10
μs
100
μs
10
1
1 ms
10 ms
100 ms
DC
10
-1
1
10
V
DS
(V)
10
2
T
mb
= 25
°C; I
DM
is single pulse
Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
Conditions
see
Figure 5
Min
-
Typ
-
Max
1.8
Unit
K/W
10
Z
th (j-mb)
(K/W)
03nm01
1
δ
= 0.5
0.2
0.1
10
-1
P
0.05
0.02
t
p
δ
=
t
p
T
t
T
10
-2
10
-6
single shot
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9Y30-75B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 10 April 2008
4 of 13
NXP Semiconductors
BUK9Y30-75B
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
Conditions
I
D
= 0.25 mA; V
GS
= 0 V;
T
j
= 25
°C
I
D
= 0.25 mA; V
GS
= 0 V;
T
j
= -55
°C
V
GS(th)
gate-source threshold I
D
= 1 mA; V
DS
= V
GS
;
voltage
T
j
= 175
°C;
see
Figure 11
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25
°C;
see
Figure 11
I
D
= 1 mA; V
DS
= V
GS
;
T
j
= -55
°C;
see
Figure 11
I
DSS
drain leakage current
V
DS
= 75 V; V
GS
= 0 V;
T
j
= 175
°C
V
DS
= 75 V; V
GS
= 0 V; T
j
= 25
°C
I
GSS
gate leakage current
V
DS
= 0 V; V
GS
= +15 V;
T
j
= 25
°C
V
DS
= 0 V; V
GS
= -15 V;
T
j
= 25
°C
R
DSon
drain-source on-state
resistance
V
GS
= 4.5 V; I
D
= 15 A; T
j
= 25
°C
V
GS
= 5 V; I
D
= 15 A; T
j
= 175
°C;
see
Figure 12
and
13
V
GS
= 5 V; I
D
= 25 A; T
j
= 25
°C
V
GS
= 5 V; I
D
= 15 A; T
j
= 25
°C;
see
Figure 12
and
13
V
GS
= 10 V; I
D
= 15 A; T
j
= 25
°C
Source-drain diode
V
SD
t
rr
Q
r
source-drain voltage
I
S
= 25 A; V
GS
= 0 V; T
j
= 25
°C;
see
Figure 16
-
-
-
0.85
101
115
1.2
-
-
V
ns
nC
Min
75
70
0.5
1.1
-
-
-
-
-
-
-
-
-
-
Typ
-
-
-
1.5
-
-
0.02
2
2
-
-
27
25
23
Max
-
-
-
2
2.3
500
1
100
100
34
72
32
30
28
Unit
V
V
V
V
V
μA
μA
nA
nA
mΩ
mΩ
mΩ
mΩ
mΩ
Static characteristics
reverse recovery time I
S
= 20 A; dI
S
/dt = -100 A/μs;
V
GS
= -10 V; V
DS
= 30 V;
recovered charge
T
j
= 25
°C
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer
capacitance
V
GS
= 0 V; V
DS
= 25 V;
f = 1 MHz; T
j
= 25
°C;
see
Figure 15
I
D
= 25 A; V
DS
= 60 V; V
GS
= 5 V;
T
j
= 25
°C;
see
Figure 14
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
-
-
-
-
-
-
19
5
9
1550
150
60
-
-
-
2070
179
80
nC
nC
nC
pF
pF
pF
BUK9Y30-75B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 10 April 2008
5 of 13
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