Low Skew, 1-to-6, Dual
Crystal/LVCMOS-to-3.3V, 2.5V LVPECL
8536-02
DATA SHEET
General Description
The 8536-02 is a low skew, high performance 1-to-6, Dual Crystal or
LVCMOS Input-to-3.3V, 2.5V LVPECL Fanout Buffer. The 8536-02
has selectable crystal or single ended clock input. The single ended
clock input accepts LVCMOS or LVTTL input levels and translates
them to LVPECL levels. The output enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
8536-02 ideal for those applications demanding well defined
performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Six 3.3V, 2.5V differential LVPECL output pairs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Maximum output frequency: 266MHz
Crystal frequency range: 14MHz – 40MHz
Output skew: 55ps (maximum)
Part-to-part skew: 500ps (maximum)
Propagation delay: 1.85ns (maximum), 3.3V
Additive phase jitter, RMS: 0.149ps (typical)
Full 3.3V or 2.5V supply modes
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in lead-free (RoHS 6) package
Block Diagram
CLK_EN
Pullup
D
Q
CLK_SEL0
Pulldown
CLK_SEL1
Pulldown
LE
Pin Assignment
nQ2
Q2
V
CC
nQ1
Q1
V
EE
nQ0
Q0
CLK_SEL0
XTAL_IN0
XTAL_OUT0
CLK_EN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q3
nQ3
V
CC
Q4
nQ4
V
CC
Q5
nQ5
CLK_SEL1
XTAL_OUT1
XTAL_IN1
CLK0
XTAL_IN0
OSC
XTAL_OUT0
XTAL_IN1
00
Q0
nQ0
6 LVPECL Outputs
OSC
XTAL_OUT1
CLK0
Pulldown
01
Q5
1X
nQ5
8536-02
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
8536-02 Rev A 7/10/15
1
©2015 Integrated Device Technology, Inc.
8536-02 DATA SHEET
Table 1. Pin Descriptions
Number
1, 2
3, 19, 22
4, 5
6
7, 8
9,
16
10,
11
12
13
14,
15
17, 18
20, 21
23, 24
Name
nQ2, Q2
V
CC
nQ1, Q1
V
EE
nQ0, Q0
CLK_SEL0,
CLK_SEL1
XTAL_IN0,
XTAL_OUT0
CLK_EN
CLK0
XTAL_IN1,
XTAL_OUT1
nQ5, Q5
nQ4, Q4
nQ3, Q3
Output
Power
Output
Power
Output
Input
Input
Input
Input
Input
Output
Output
Output
Pullup
Pulldown
Pulldown
Type
Description
Differential output pair. LVPECL interface levels.
Power supply pins.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Clock select pins. LVCMOS/LVTTL interface levels. See Table 3B.
Parallel resonant crystal interface.
XTAL_OUT0 is the output, XTAL_IN0 is the input.
Synchronizing clock enable. When HIGH, clock outputs follow clock input. When
LOW, the outputs are disabled. LVCMOS / LVTTL interface levels. See Table 3A.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface.
XTAL_OUT1 is the output, XTAL_IN1 is the input.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
LOW SKEW, 1-TO-6, DUAL CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FANOUT BUFFER
2
Rev A 7/10/15
8536-02 DATA SHEET
Function Tables
Table 3. Control Input Function Table
Inputs
CLK_EN
0
0
0
1
1
1
CLK_SEL1
0
0
1
0
0
1
CLK_SEL0
0
1
X
0
1
X
Selected Source
XTAL0
XTAL1
CLK0
XTAL0
XTAL1
CLK0
Q[0:5]
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Outputs
nQ[0:5]
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 1.
In the active mode, the state of the outputs are a function of the selected clock input.
Disabled
Enabled
CLK0,
XTAL0, XTAL1
CLK_EN
nQ[0:5]
Q[0:5]
Figure 1. CLK_EN Timing Diagram
Rev A 7/10/15
3
LOW SKEW, 1-TO-6, DUAL CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FANOUT BUFFER
8536-02 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
XTAL_IN
Other Input
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
CC
-0.5V to V
CC
+ 0.5V
50mA
100mA
87.8C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
I
EE
Parameter
Core Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
89
Units
V
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
I
EE
Parameter
Core Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
84
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,
T
A
= 0°C to 70°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
Input Low Voltage
Input
High Current
CLK0, CLK_SEL[0:1]
CLK_EN
CLK0, CLK_SEL[0:1]
I
IL
Input
Low Current
CLK_EN
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
-5
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
IL
I
IH
LOW SKEW, 1-TO-6, DUAL CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FANOUT BUFFER
4
Rev A 7/10/15
8536-02 DATA SHEET
Table 4D. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
C C
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
Table 4E. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.4
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.5
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
14
Test Conditions
Minimum
Typical
Fundamental
40
50
7
MHz
Maximum
Units
pF
Rev A 7/10/15
5
LOW SKEW, 1-TO-6, DUAL CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL
FANOUT BUFFER
嵌入式系统
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