Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Datasheet
Advance Information
Product Features
s
s
s
s
High Performance Processor based on
Intel
®
XScale
™
Microarchitecture
— 7-8 stage Intel
®
Superpipelined
Technology
— 32-Entry Instruction Memory
Management Unit
— 32-Entry Data Memory Management
Unit
— 32 KByte, 32-way Set Associative
Instruction Cache
— 32 KByte, 32-way Set Associative Data
Cache
— 2 KByte, 2-way Set Associative
Mini-Data Cache
— 128-Entry Branch Target Buffer
— 8-Entry Write Buffer
— 4-Entry Fill and Pend Buffers
Intel
®
Dynamic Voltage Management
— Core Voltage Range: 0.95 V to 1.55 V
— Internal Clock Scalable by Software up
to 733 MHz
— Input Clock: 33-66 MHz
ARM* Version 5TE Compliant
Application-Code Compatible with
Intel
®
StrongARM* SA-110
s
s
s
s
s
Power Management
— Less than 750mW at 333MHz
— Core Voltage may be Operated Down to
0.95 V
— Idle, Drowsy and Sleep Modes
Intel
®
Media Processing Technology
— Multiply-Accumulate Coprocessor
High Performance External Bus
— 64- or 32-Bit Data Interface
— Optional ECC Protection
— Frequency up to 100 MHz
— Asynchronous to Processor Clock
Performance Monitoring Unit
— Two 32-Bit Event Counters
— One 32-Bit Clock Counter
— Monitors Occurrence and Duration
Events
Debug Unit
— Accessible through JTAG Port
— Hardware Breakpoints
— 256-Entry Trace Buffer
Notice:
This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.
September 2000
Reference Number: 273414-001
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright© Intel Corporation, 2000
*Other brands and names are the property of their respective owners.
2
September 2000
Advance Information
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture Datasheet
Contents
1.0
2.0
About this Document ..........................................................................................................5
Functional Overview........................................................................................................... 5
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
3.0
Superpipeline ........................................................................................................ 7
Branch Target Buffer (BTB)................................................................................... 8
Instruction Memory Management Unit (IMMU) ..................................................... 8
Data Memory Management Unit (DMMU) .............................................................9
Instruction Cache (I-Cache) .................................................................................. 9
Data Cache (D-Cache)........................................................................................ 10
Mini-Data Cache.................................................................................................. 10
Fill Buffer (FB) and Pend Buffer (PB) ..................................................................11
Write Buffer (WB) ................................................................................................ 11
Multiply-Accumulate Coprocessor (CP0) ............................................................ 11
Clock and Power Management ........................................................................... 12
Performance Monitoring Unit (PMU) ................................................................... 12
Debug Unit .......................................................................................................... 12
Package Information ........................................................................................................13
3.1
Package Introduction........................................................................................... 13
3.1.1 Functional Signal Definitions ..................................................................13
3.1.1.1 Signal Pin Descriptions ............................................................. 13
3.1.2 241 Lead PBGA Package ...................................................................... 17
Package Thermal Specifications .........................................................................22
Package Thermal Resistance ............................................................................. 22
3.2
3.3
4.0
Electrical Specifications.................................................................................................... 24
4.1
4.2
4.3
Absolute Maximum Ratings................................................................................. 24
Targeted DC Specifications................................................................................. 25
Targeted AC Specifications................................................................................. 26
4.3.1 Clock Signal Timings ..............................................................................26
4.3.2 Bus Signal Timings................................................................................. 27
4.3.3 Boundary Scan Test Signal Timings ...................................................... 28
AC Timing Waveforms ........................................................................................ 29
Power Sequence .................................................................................................31
Reset Timing ....................................................................................................... 33
AC Test Conditions ............................................................................................. 33
Power Dissipation................................................................................................ 34
4.4
4.5
4.6
4.7
4.8
September 2000
Advance Information
3
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture Datasheet
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Intel
®
80200 Processor Block Diagram ................................................................. 6
241-Lead PBGA Package ................................................................................... 17
Case Temperature with No Air Flow ................................................................... 23
Case Temperature at Nominal Power Dissipation .............................................. 23
CLK Waveform .................................................................................................... 29
MCLK Waveform ................................................................................................. 29
T
OV
Output Delay Waveform .............................................................................. 30
Correct Power Sequence for V
CC
, V
CCP
............................................................. 31
Another Correct Power Sequence for V
CC
, V
CCP
............................................... 31
Incorrect Power Sequence for V
CC
, V
CCP
........................................................... 31
Preferred Power Sequence for VCC, VCCa ....................................................... 32
Correct Power Sequence for VCC, VCCa........................................................... 32
Pins’ State at Reset............................................................................................. 33
AC Test Load ...................................................................................................... 33
Pin Power Dissipation ......................................................................................... 34
Core Power Dissipation....................................................................................... 34
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Related Documentation......................................................................................... 5
Pin Description Nomenclature............................................................................. 13
Power Pins .......................................................................................................... 14
Signal Pin Description ......................................................................................... 14
JTAG Pins ........................................................................................................... 16
241-Lead PBGA Pinout — Ballpad Number Order ............................................. 18
241-Lead PBGA Pinout — Signal Name Order .................................................. 20
Package Thermal Resistance — °C/Watt ........................................................... 22
Operating Conditions .......................................................................................... 24
Voltage Range Requirements for Different Intel
®
80200 Processor
Product Options .................................................................................................. 24
DC Characteristics .............................................................................................. 25
I
CC
Characteristics .............................................................................................. 25
Input Clock Timings............................................................................................. 26
Output Timings .................................................................................................... 27
Input Timings....................................................................................................... 27
Boundary Scan Test Signal Timings ................................................................... 28
4
September 2000
Advance Information
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture Datasheet
About this Document
1.0
About this Document
This is the Advance Information data sheet for the Intel
®
80200 processor based on Intel
®
XScale
™
microarchitecture (ARM* architecture compliant). This data sheet contains a functional overview,
mechanical data (package signal locations and simulated thermal characteristics), targeted
electrical specifications (simulated), and bus functional waveforms. Detailed functional
descriptions other than parametric performance is published in the
Intel
®
80200 Processor based
on Intel
®
XScale
™
Microarchitecture Developer’s Manual.
Table 1.
Related Documentation
Document Title
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture Specification Update
Intel
®
80310 I/O Processor Chipset Design Guide
Intel
®
80312 I/O Companion Chip Developer’s Manual
Intel
®
80312 I/O Companion Chip Datasheet
Intel
®
80312 I/O Companion Chip Specification Update
Document #
273411
273415
273354
273410
273425
273416
2.0
Functional Overview
The Intel
®
80200 processor technology is compliant with the ARM* Version 5TE instruction set
architecture (ISA). The Intel
®
80200 processor is designed with Intel state-of-the-art 0.18 micron
production semiconductor process technology. This process technology, along with the
compactness of the ARM RISC ISA, enables the Intel
®
80200 processor to operate over a wide
speed/power range, producing industry-leading mW/MIPS performance.
•
7-8 stage Superpipeline promotes high speed, efficient core performance
•
128-entry Branch Target Buffer keeps pipeline filled with statistically correct branch choices
•
32-entry Instruction Memory Management Unit for logical-to-physical address translation,
access permissions, I-Cache attributes
•
32-entry Data Memory Management Unit for logical-to-physical address translation, access
permissions, D-Cache attributes
•
32 KB Instruction Cache can hold entire programs, preventing core stalls caused by multicycle
memory accesses
•
32 KB Data Cache reduces core stalls caused by multicycle memory accesses
•
2 KB Minidata Cache for frequently changing data streams avoids “thrashing” of the D-Cache
•
4-entry Fill and Pend Buffers promote core efficiency by allowing “hit-under- miss” operation
with Data Caches
•
Power Management Unit gives power savings via idle, drowsy, and sleep modes
•
8-entry Write Buffer allows the core to continue execution while data is written to memory
•
Multiply-Accumulate Coprocessor can do two simultaneous 16-bit SIMD multiplies with
40-bit accumulation for efficient, high quality audio
September 2000
5
Advance Information
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
