Differential-to-0.7V Differential PCI Express
™
Jitter Attenuator
ICS871S1022
DATASHEET
Description
IDT’s PLL-based clock generators offer sub-picosecond jitter,
low-skew clock outputs, and edge rates that meet the ever-growing
demands of today’s networking solutions.
The ICS871S1022 is a PLL-based clock generator specifically
designed for PCI Express Clock Generation applications. The device
generates 100MHz, 125MHz, 250MHz or 500MHz from either a
25MHz fundamental mode crystal or a 100MHz recovered clock.
The ICS871S1022 has two modes of operation: (1) high frequency
jitter attenuator and (2) high performance clock synthesizer mode.
When in jitter attenuator mode, the ICS871S1022 is able to both
suppress high frequency noise components and function as a
frequency translator. Designed to receive a jittery and noisy clock
from an external source, the ICS871S1022 uses FemtoClock
®
technology to clean up the incoming clock and translate the
frequency to one of the four common PCI Express frequencies.
When in synthesizer mode, the device is able to generate high
performance SSC and non-SSC clocks from a low cost external,
25MHz, fundamental mode crystal.
The ICS871S1022 uses FemtoClock
®
technology to generate low
noise clock outputs capable of providing the seed frequencies for the
common PCI Express link rates.
Features
•
•
•
•
•
•
•
•
•
•
•
Four 0.7V differential output pairs
One differential clock input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
Crystal oscillator interface designed for 25MHz, 18pF parallel
resonant crystal
RMS phase jitter at 100MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.608ps (typical)
High frequency jitter attenuator mode has high PLL bandwidth
which allows for better input tracking
Supports PCI Express Spread-Spectrum Clocking
PCI Express Gen 1, 2 and 3 jitter compliant
3.3V operating supply voltage
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
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©2017 Integrated Device Technology, Inc.
ICS871S1022 Datasheet
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Block Diagram
100MHz
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©2017 Integrated Device Technology, Inc.
ICS871S1022 Datasheet
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Table 1. Pin Descriptions
Number
1, 17
2
3
4
5,
6
7
8, 12, 20, 28
9, 16, 25, 32
10, 11
13
14,15
18, 19
21
22
23
24
26, 27
29
30, 31
Name
V
DD
CLK
nCLK
V
DD_XTAL
XTAL_IN,
XTAL_OUT
CLK_SEL
GND
V
DDO
QB0, nQB0
OEB
QB1, nQB1
N1, N0
V
DDA
SSC_EN
PLL_SEL
IREF
nQA1, QA1
OEA
nQA0, QA0
Power
Input
Input
Power
Input
Input
Power
Power
Output
Input
Output
Input
Power
Input
Input
Output
Output
Input
Output
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pullup
Pulldown
Pullup/
Pulldown
Type
Description
Core supply pins.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
DD
/2.
Crystal oscillator supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal
circuit with a single-ended or differential reference clock.
Input source control pin and device operation control pin. See Table 3C.
LVCMOS/LVTTL interface levels.
Power supply ground.
Output power supply pins.
Differential output pair. HCSL interface levels.
Output enable pin for QB, nQB[0:1] pins. When HIGH, the outputs are active.
When LOW, the outputs are in high-impedance state. See Table 3A.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Output divider control pins. See Table 3D for additional information.
LVCMOS/LVTTL interface levels.
Analog supply pin.
SSC enable pin. See Table 3B. LVCMOS/LVTTL interface levels.
PLL Bypass control pin. LVCMOS/LVTTL interface levels.
HCSL current reference resistor output. An external fixed precision resistor
(475
) from this pin to ground provides a reference current used for
differential current-mode Qx, nQx clock outputs.
Differential output pair. HCSL interface levels.
Output enable pin for QA, nQA[0:1] pins. When HIGH, the outputs are active.
When LOW, the outputs are in a high-impedance state. See Table 3A.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
5
51
51
Maximum
Units
pF
k
k
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©2017 Integrated Device Technology, Inc.
ICS871S1022 Datasheet
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Function Tables
Table 3A. PLL_SEL Function Table
Inputs
0
1
Reference
PLL_SEL
PLL_SEL
Mode
Bypass
PLL
Table 3B. Output Enable Function Table
Inputs
OEA, OEB
0
1
Outputs
QA[0:1], nQA[0:1]
High-Impedance
Enabled
QB[0:1], nQB[0:1]
High-Impedance
Enabled
Table 3C. SSC Enable Function Table
Inputs
SSC_EN
0
1
Outputs
Qx[0:1], nQx[0:1]
SSC Disabled
-0.37% downspread
Table 3D. CLK_SEL Function Table
Input
CLK_SEL
0
1
Reference
CLK, nCLK
XTAL_IN, XTAL_OUT
Mode
High Frequency Jitter Attenuator
Clock Synthesizer
Table 3E. Output Frequency Configuration Table
Inputs
CLK_SEL
0
0
0
0
1
1
1
1
Input Frequency (MHz)
100
100
100
100
25
25
25
25
N1:N0
00
01
10
11
00
01
10
11
N Divider Value
5
4
2
1
5
4
2
1
Output Frequency (MHz)
PLL_SEL = 1
100
125
250
500
100
125
250
500
PLL_SEL = 0
20
25
50
100
5
6.25
12.5
25
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©2017 Integrated Device Technology, Inc.
ICS871S1022 Datasheet
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD_XTAL
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
39.5C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= V
DD_XTAL
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DD_XTAL
V
DDA
V
DDO
I
DD
I
DD_XTAL
I
DDA
I
DDO
Parameter
Core Supply Voltage
Crystal Supply Voltage
Analog Supply Voltage
Power Supply Voltage
Power Supply Current
Crystal Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
V
DD
– 0.18
3.135
Typical
3.3
3.3
3.3
3.3
Maximum
3.465
3.465
V
DD
3.465
100
7
18
27
Units
V
V
V
V
mA
mA
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= V
DD_XTAL
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
SSC_EN, N0, N1
Input High Current
OEA, OEB,
PLL_SEL, CLK_SEL
SSC_EN, N0, N1
I
IL
Input Low Current
OEA, OEB,
PLL_SEL, CLK_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-10
-150
Test Conditions
Minimum
2.2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
10
Units
V
V
μA
μA
μA
μA
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©2017 Integrated Device Technology, Inc.
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