32Mx72 bits
Unbuffered DDR SDRAM DIMM
HYMD232726D(L)8J-D43/D4/J
Document Title
32M x 72 bits Unbuffered DDR SDRAM DIMM
Revision History
No.
0.1
0.2
History
Draft Date
Apr. 2003
May. 2004
Remark
Initial Draft
Corrected some typos.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / May 2004
1
32Mx72 bits
Unbuffered DDR SDRAM DIMM
HYMD232726D(L)8J-D43/D4/J
DESCRIPTION
Hynix HYMD232726D(L)8J-D43/D4/J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as 32M x 72 high-speed memory arrays. Hynix HYMD232726D(L)8J-
D43/D4/J series consists of nine 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate.
Hynix HYMD232726D(L)8J-D43/D4/J series provide a high performance 8-byte interface in 5.25" width form factor of
industry standard. It is suitable for easy interchange and addition.
Hynix HYMD232726D(L)8J-D43/D4/J series is designed for high speed of up to 166/200MHz and offers fully synchro-
nous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control
inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on
both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable
latencies and burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD232726D(L)8J-D43/D4/J series incorporates SPD(serial presence detect). Serial presence detect function
is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to iden-
tify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
•
•
•
256MB (32M x 72) Unbuffered DDR DIMM based on
32Mx8 DDR SDRAM
JEDEC Standard 184-pin dual in-line memory module
(DIMM)
Error Check Correction (ECC) Capability
2.5V +/- 0.2V VDD and VDDQ Power supply for
DDR333 and 2.6V +/- 0.1V VDD and VDDQ for
DDR400
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock operations (CK & /CK) with
166/200MHz
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
•
•
•
•
•
•
•
•
•
Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
Data inputs on DQS centers when write (centered
DQ)
Data strobes synchronized with output data for read
and input data for write
Programmable CAS Latency 3 for DDR400, 2.5 for
DDR333 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
tRAS Lock-out function supported
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
•
•
•
ORDERING INFORMATION
Part No.
HYMD232726D(L)8J-D43
HYMD232726D(L)8J-D4
HYMD232726D(L)8J-J
Power Supply
V
DD
=V
DDQ
=2.6V
V
DD
=V
DDQ
=2.5V
Clock Frequency
200MHz (DDR400 3-3-3)
200MHz (DDR400 3-4-4)
166MHz (DDR333 2.5-3-3)
Interface
Form Factor
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
SSTL_2
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / May 2004
2
HYMD232726D(L)8J-D43/D4/J
PIN DESCRIPTION
Pin
CK0,/CK0,CK1,/CK1,CK2,/CK2
CS0
CKE0
/RAS, /CAS, /WE
A0 ~ A12
BA0, BA1
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DM0~DM8
VDD
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Bank Address
Data Inputs/Outputs
Check Bit
Data Strobe Inputs/Outputs
Data-in Mask
Power Supply
Pin
VDDQ
VSS
VREF
VDDSPD
SA0~SA2
SCL
SDA
WP
VDDID
DU
NC
Pin Description
DQs Power Supply
Ground
Reference Power Supply
Power Supply for SPD
E
2
PROM Address Inputs
E
2
PROM Clock
E
2
PROM Data I/O
Write Protect Flag
VDD Identification Flag
Do not Use
No Connection
PIN ASSIGNMENT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
53
54
55
56
57
58
59
60
61
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Key
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
Name
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
Vss
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Name
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
/CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Name
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1*
VDDQ
BA2*
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
145
146
147
148
149
150
151
152
153
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
key
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
Name
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8
A10
CB6
VDDQ
CB7
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Name
/RAS
DQ45
VDDQ
/CS0
/CS1*
DM5
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
A13*
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
* These are not used on this module but may be used for other module in 184pin DIMM family
Rev. 0.2 / May 2004
3
HYMD232726D(L)8J-D43/D4/J
FUNCTIONAL BLOCK DIAGRAM
/C S 0
DQS0
D M 0/D Q S 9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
/CS
DQ S
D Q S4
D M 4/D Q S 13
D Q 32
D Q 33
D Q 34
D Q 35
D Q 36
D Q 37
D Q 38
D Q 39
DM
I/O 0
I/O 1
I/O 2
/CS
DQS
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQS1
D M 1/D Q S 10
DQ8
DQ9
D Q 10
D Q 11
D Q 12
D Q 13
D Q 14
D Q 15
DM
I/O 0
I/O 1
I/O 2
/CS
DQ S
DQS5
D M 5/D Q S 14
D Q 40
D Q 41
D Q 42
D Q 43
D Q 44
D Q 45
D Q 46
D Q 47
DM
I/O 0
I/O 1
I/O 2
/CS
DQS
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS2
D M 2/D Q S11
D Q S6
D M 6/D Q S15
DM
I/O 0
I/O 1
I/O 2
/CS
DQ S
D Q 16
D Q 17
D Q 18
D Q 19
D Q 20
D Q 21
D Q 22
D Q 23
DQS3
D M 3/D Q S 12
D Q 24
D Q 25
D Q 26
D Q 27
D Q 28
D Q 29
D Q 30
D Q 31
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D Q 48
D Q 49
D Q 50
D Q 51
D Q 52
D Q 53
D Q 54
D Q 55
DM
I/O 0
I/O 1
I/O 2
/CS
DQS
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQS7
D M 7/D Q S 16
DM
I/O 0
I/O 1
I/O 2
/CS
DQ S
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D Q 56
D Q 57
D Q 58
D Q 59
D Q 60
D Q 61
D Q 62
D Q 63
VD D SPD
VDD /VD D Q
SPD
DM
I/O 0
I/O 1
I/O 2
/CS
DQS
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
DQS3
D M 3/D Q S 12
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 0
I/O 1
I/O 2
/CS
DQ S
*C lock W iring
D O -D 8
D O -D 8
D O -D 8
Strap:see Note 4
Clock Input
SD R AM s
VR EF
VSS
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
*C K0, /CK0
*C K1, /CK1
*C K2, /CK2
3 SD R AM s
3 SD R AM s
3 SD R AM s
VD D ID
Serial PD
SCL
W
P
*W ire per C lock Loading
Table/W iring Diagram s
SD A
A0
A1
A2
B A 0-B A 1
A 0-A 13
/R A S
/CA S
C K E0
/W E
B A 0-B A 1 : SD R A M s D 0-D 8
A0-A 13 : SD R A M s D0-D 8
/RA S : SD RA M s D 0-D8
/C A S : SD R A M s D 0-D 8
C KE : SD R AM s D 0-D 8
/W E : SDR A M s D 0-D 8
SA 0 SA 1 SA 2
Notes :
1. DQ -to-I/O w iring is show n as recom m ended but
m ay be changed.
2. DQ /DQ S /DM /C KE /S relationships m ust be
m aintained as show n.
3. DQ , DQ S, DM /DQ S resistors : 22 O hm s + - 5% .
4. V DDID strap connections
(for m em ory device VDD , V DDQ ):
STRAP O UT (O PEN) : VDD = VD DQ
STR A P IN (VS S ) : VD D
≠
V D D Q
5. BA x, Ax, R AS , CAS , W E resistors : 5.1 O hm s +- 5%
Rev. 0.2 / May 2004
4
HYMD232726D(L)8J-D43/D4/J
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature (Ambient)
Storage Temperature
Voltage on Inputs relative to V
SS
Voltage on I/O Pins relative to V
SS
Voltage on V
DD
relative to V
SS
Voltage on V
DDQ
relative to V
SS
Output Short Circuit Current
Power Dissipation
Soldering Temperature Þ Time
T
A
T
STG
V
IN
V
IO
V
DD
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
1.0 x # of Components
260 / 10
Rating
o
o
Unit
C
C
V
V
V
V
mA
W
o
C / Sec
Note
:
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Power Supply Voltage
Power Supply Voltage
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
V
DD
V
DD
V
DDQ
V
DDQ
V
IH
V
IL
V
TT
V
REF
Symbol
Min
2.3
2.5
2.3
2.5
V
REF
+ 0.15
-0.3
V
REF
- 0.04
0.49*V
DDQ
Typ.
2.5
2.6
2.5
2.6
-
-
V
REF
0.5*V
DDQ
Max
2.7
2.7
2.7
2.7
V
DDQ
+ 0.3
V
REF
- 0.15
V
REF
+ 0.04
0.51*V
DDQ
Unit
V
V
V
V
V
V
V
V
3
2
4
1
1,4
Note
Note :
1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
4. For DDR400, VDD=2.6V +/- 0.1V, VDDQ=2.6V+/-0.1V
Rev. 0.2 / May 2004
5
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