DATASHEET
SPREAD SPECTRUM CLOCK GENERATOR
Description
The MK1726-08 generates a low EMI output clock and a
reference clock from a clock or crystal input. The part is
designed to lower EMI through the application of spreading
a clock. Using IDT’ proprietary mix of analog and digital
Phase-Locked Loop (PLL) technology, the device spreads
the frequency spectrum of the output, reducing the
frequency amplitude peaks by several dB depending on
spread range. The MK1726-08 offers a range of down
spread from a high speed clock or crystal input. The
MK1726-08 generates one modulated (SSCLK) and
unmodulated (REFCLK) clock and is compatible with
Cypress CY25819. The modulated clock is controlled by
the select pin, and the unmodulated clock has the same
frequency as the input clock or crystal.
MK1726-08
Features
•
•
•
•
•
•
•
•
Packaged in 8-pin SOIC
Available in Pb (lead) free package
Input frequency range 16- 32 MHz
Provides modulated and unmodulated clocks
Accepts a clock or crystal input
Provides down spread modulation
Provides power down function
Reduce electromagnetic interference (EMI) by
8-16 db
•
Operating voltage of 3.3 V
•
Advanced, low-power CMOS process
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
VDD
PD
S0
PLL Clock
Synthesis and
Spread
Spectrum
Circuitry
REFCLK
X1/CLK
Clock Buffer/
Crystal
Ocsillator
X2
External caps required for
with crystal for accurate
tuning of the clock
SSCLK
GND
IDT™
SPREAD SPECTRUM CLOCK GENERATOR
1
MK1726-08
REV C 121809
MK1726-08
SPREAD SPECTRUM CLOCK GENERATOR
SSCG
Pin Assignment
X1/ICLK
GND
S0
SSCLK
1
2
3
4
8
7
6
5
X2
VDD
PD
REFCLK
Spread Percentage Select Table
S0
0
1
M
Spread
Direction
Down
Down
Down
Spread
Percentage (%)
-1.8
-2.5
-0.6
8 p i n ( 1 5 0 mi l ) S O I C
0 = connect to GND
M= unconnected
1 = connect directly to VDD
* Default has internal pull up resitor to VDD
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Pin Description
1
2
3
4
5
6
7
8
X1/ICLK
GND
S0
SSCLK
REFCLK
PD
VDD
X2
Input
Power
Input
Output
Power
Input
Power
Input
Connect to 16-32 MHz crystal or clock.
Connect to ground.
Select spread percentage per table above. Internal pull-up.
Spread spectrum clock output per table above.
CMOS level clock output matches the nominal frequency of the input crystal or
clock.
Power down tri-state. This pin powers down entire chip and tri-state the outputs
when low. Internal pull-up.
Connect to 3.3 V.
Connect to 16-32 MHz crystal or leave unconnected.
IDT™
SPREAD SPECTRUM CLOCK GENERATOR
2
MK1726-08
REV C 121809
MK1726-08
SPREAD SPECTRUM CLOCK GENERATOR
SSCG
External Components
The MK1726-08 requires a minimum number of external
components for proper operation.
is given by the following equation:
Crystal caps (pF) = (C
L
- 6) x 2
In the equation, C
L
is the crystal load capacitance. So, for a
crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2]
capacitors should be used.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Spread Spectrum Profile
The MK1726-08 low EMI clock generator uses an optimized
frequency slew rate algorithm to facilitate down stream
tracking of zero delay buffers and other PLL devices. The
frequency modulation amplitude is constant with variations
of the input frequency.
Series Termination Resistor
When the PCB trace between the clock output and the load
is over 1 inch, series termination should be used. To series
terminate a 50Ω trace (a commonly used trace impedance)
place a 33Ω resistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20Ω
.
Modulation R
ate
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
MK1726-08. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
Frequency
Time
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
IDT™
SPREAD SPECTRUM CLOCK GENERATOR
3
MK1726-08
REV C 121809
MK1726-08
SPREAD SPECTRUM CLOCK GENERATOR
SSCG
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1726-08. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+2.97
Typ.
Max.
+70
3.63
Units
°
C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V +10%,
Ambient Temperature 0 to +70° C
Parameter
Power Supply Range
Input High Voltage
Input Middle Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage
Power Supply Current
Power Supply Current
Symbol
V
DD
V
INH
V
INM
V
INL
V
OH1
V
OH2
V
OL1
V
OL2
I
DD2
I
DD3
Conditions
S0 Input
S0 Input
S0 Input
I
OH
=4 ma, SSCLK
and REFCLK
I
OH
=6 ma, SSCLK
and REFCLK
I
OL
=4 ma, SSCLK
I
OL
=10 ma, SSCLK
F
IN
=32 MHz, no load
PD = GND
Min.
2.97
0.85 V
DD
0.40 V
DD
0.0
2.4
2.0
Typ.
3.3
V
DD
0.50 V
DD
0.0
Max.
3.63
V
DD
0.60 V
DD
0.15 V
DD
Units
V
V
V
V
V
V
0.4
1.2
19.0
150
23.0
250
V
V
mA
uA
IDT™
SPREAD SPECTRUM CLOCK GENERATOR
4
MK1726-08
REV C 121809
MK1726-08
SPREAD SPECTRUM CLOCK GENERATOR
SSCG
Parameter
Input Capacitance
clock output
impedance
Internal pull-up
resistor
Symbol
C
IN
Conditions
Min.
Typ.
5
20
Max.
Units
pF
ohms
kΩ
R
PU
SEL
360
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V +10%,
Ambient Temperature 0 to +70° C
Parameter
Input Clock Frequency
Output Clock Frequency
Clock Rise Time
Clock Fall Time
Input Clock Duty Cycle
Output Clock Duty Cycle
Cycle-to-Cycle Jitter
Symbol
Conditions
Min.
16
16
Typ.
Max. Units
32
32
MHz
MHz
ns
ns
%
%
ps
trise1
tfall1
SSCLK and REFCLK,
0.4 V to 2.4 V
SSCLK and REFCLK,
0.4 V to 2.4 V
X
1
SSCLK and REFCLK
@1.5V
SSCLK,
Fin=21MHz,
Fout=21MHz
REFCLK,
Fin=21MHz,
Fout=21MHz
2.0
2.0
20
45
3.0
3.0
50
50
250
4.0
4.0
80
55
350
Cycle-to-Cycle Jitter
275
375
ps
EMI Peak Frequency Reduction
8 to 16
dB
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
110
100
80
35
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
IDT™
SPREAD SPECTRUM CLOCK GENERATOR
5
MK1726-08
REV C 121809
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