MN101D02D , MN101D02F , MN101D02G ,
MN101D02H
Type
ROM (×8-bit)
×
RAM (×8-bit)
×
Package
Minimum Instruction
Execution Time
Interrupts
With main clock operated
When sub-clock operated
MN101D02D
72 K
2K
MN101D02F
96 K
3K
QFP100-P-1818B
*Pb free
MN101D02G
128 K
4K
VTR Servo
MN101D02H
160 K
5K
0.1397
µs
(at 4.0 V to 5.5 V, 14.32 MHz)
71.5
µs
(at 2.2 V to 5.5 V fixed to 14.32 MHz internal frequency division)
61
µs
(at 2.2 V to 5.5 V, 32.768 kHz)
• RESET • Runaway • External 0, 1, 2, 3, 4/key input (P50 to 54) • Timer 0 • Timer 1 • Timer 2 • Timer 3
• Timer 4 • Timer 6 • Capstan FG • Control • HSW • Cylinder FG • Servo VSYNC • Synchronous output
• OSD • XDS • Serial 0 • Serial 1 • Serial 2 • A/D (common with PWM 14 reference frequency)
• OSDVSYNC
Timer counter 0: 16-bit
×
1
(timer function, clock function [max. 2 s or max. 36 h at cascade-connecting with timer 6])
Clock source ····················· 1/2, 1/4, 1/8, 1/16 of system clock frequency; overflow of timer counter 6;
1/512 of XI oscillation clock or OSC oscillation clock frequency
Interrupt source ················ overflow of timer counter 0
Timer counter 1: 16-bit
×
1 (timer function, linear timer counter function)
Clock source ····················· 1/2, 1/4, 1/8, 1/16 of system clock frequency; CTL signal
Interrupt source ················ overflow of timer counter 1
Timer counter 2: 16-bit
×
1 (timer function, input capture (DCTL specified edge), duty judgment of DCTL
signal)
Clock source ····················· 1/2, 1/4, 1/8, 1/12, 1/16, 1/24 of system clock frequency
Interrupt source ················ overflow of timer counter 2; input of DCTL specified edge; underflow of timer
2 shift register 4-bit counter; coincidence of timer 2 shift register with timer 2
shift register compare register
Timer counter 3: 16-bit
×
1
(timer function, detection of serial indexing, generation of remote control output carrier frequency)
Clock source ····················· 1/2, 1/4, 1/8, 1/16 of system clock frequency
Interrupt source ················ overflow of timer counter 3
Timer counter 4: 16-bit
×
1 (timer function, event count [P15 input], generation of serial transmission clock)
Clock source ····················· 1/8, 1/16 of system clock frequency; external clock input
Interrupt source ················ overflow of timer counter 4; coincidence of timer counter 4 with OCR4
Timer counter 5: 19-bit
×
1 (watchdog, stable oscillation waiting function)
Clock source ····················· system clock
Watchdog interrupt source ······· 1/2
16
, 1/2
19
of timer counter 5 frequency
Clear by stable oscillation ········ after 256 counts by timer counter 5 (2
18
counts of OSC oscillation clock)
Timer counter 6: 16-bit
×
1 (clock function [max. 2 s])
Clock source ····················· 1/512 of OSC oscillation clock frequency; XI oscillation clock;
1/4, 1/8, 1/64, 1/128 of system clock frequency
Interrupt source ················ 1/2
13
, 1/2
14
, 1/2
15
overflow of timer counter 6
Timer Counter
Serial Interface
Serial 0: 8-bit
×
1 (synchronous type/start-stop synchronous type) (transfer direction of MSB/LSB selectable)
Synchronous type clock source · 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 of system clock frequency;
2-division timer 4 output; SBT0 pin input
Clock for UART ··············· 8-division of above clock; 2-division timer 4 output; SBT0 pin input
Serial 1: 8-bit
×
1
(synchronous type/remote control transmission/simple remote control receive) (transfer direction of MSB/LSB
selectable, start condition function)
Clock source ····················· 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 of system clock frequency;
2-division timer 4 output; SBT1 pin input
Remote control clock ······ 2-division timer 4 output
102
MAD00028BEM
MN101D02D , MN101D02F , MN101D02G
MN101D02H
Serial Interface (Continue)
Serial 2: 8-bit
×
1 (I
2
C) (master transmission/reception, slave transmission/reception)
Clock source ····················· 1/72, 1/80, 1/84, 1/96, 1/102, 1/112, 1/128, 1/144, 1/160, 1/168,
1/192, 1/224, 1/256, 1/320 of system clock; SCK pin input
Accommodation with menu or super impose display
Applicable broadcasting system
: NTSC, PAL, PAL-M, PAL-N
Screen configuration
: 24 characters
×
2n rows (n = 1 to 6)
Character type
: max. 512 character types (variable)
Character size
: 12
×
18 dots
Enlarged characters
: each
×
2,
×
3 or
×
4 settings in horizontal and vertical
Character interpolation
: none
Background color
: 8-hue settable (settable in the row unit at menu display)
Background intensity
: 8 gradations settable in the row unit
Character color
: white
Character intensity
: 8 gradations settable in the row unit
Frame function
: 1-dot frame in 4 or 8 directions
Frame intensity
: 4 gradations settable in the row unit
Box shade function
: settable in the character unit (only at composite output with 128 character
types or more)
Blinking
: none (covered by software)
Inverted character
: settable in the character unit
Halftone
: settable in the row unit in 2 intensity gradations (setting in the row unit)
Input
: composite video signal input (output level: 1 V[p-p] / 2 V[p-p])
Clamp method
: sync chip clamp, clamp level in 4 levels
Output
: composite video output
: digital output (6 pins)
8 character and background colors each settable at digital output.
Measure against image fluctuation : built-in AFC circuit
Sync signal detection function
: detection functions for horizontal and vertical sync signals (integral system)
with horizontal sync signal interpolation function
Built-in U.S. closed caption data slicer (optional 2 line data can be extracted.)
Correcting address designation: up to 2 addresses possible
Correction method: correction program being saved in internal RAM
OSD
XDS
ROM Correction
I/O Pins
A/D Inputs
PWM
I/O
Input
73
4
• Common use: 73 ports 0, 1, 2, 4, 5, 6, 7, A, B (by bit)
• Common use: 4
8-bit
×
12-ch. (without S/H)
13-bit
×
2-ch. (at repetition cycle 572
µs,
14.32 MHz),
10-bit
×
2-ch. (at repetition cycle 71.5
µs,
14.32 MHz),
14-bit
×
1-ch. (at repetition cycle 1144
µs,
14.32 MHz)
18-bit
×
6-ch.
16-bit
×
7-ch. , 8-bit
×
1-ch.
Buzzer output; 3-state output (PTO) VLP pin; synchronous output: 7; 3-state synchronous output: 4;
remote control receive; CTL amp; built-in FG amp;
output of 1/2 OSC oscillation clock (2 V[p-p]); output of 1/4 OSC oscillation clock (1 V[p-p])
VISS/VASS detection function
ICR
OCR
Special Ports
Notes
See the next page for electrical characteristics, pin assignment and support tool.
MAD00028BEM
103
Electrical Characteristics
Supply current
Limit
Parameter
Symbol
IDD1
Operating supply current
IDD2
IDD3
32 kHz oscillation operation without load
Supply current at STOP
IDSP
IDHT0
Supply current at HALT
IDHT1
32 kHz oscillation operation without load
Stop of oscillation without load, VDD = 5 V
14.32 MHz oscillation without load, VDD = 5 V
Stop of 14.32 MHz oscillation, VDD = 2.7 V
5
20
0
5
20
15
Condition
min
14.32 MHz operation without load, VDD = 5 V
1/1024 of 14.32 MHz operation without load, VDD = 2.7 V
Stop of 14.32 MHz oscillation, VDD = 2.7 V
50
100
typ
60
2
max
100
5
mA
mA
µ
A
µ
A
mA
µ
A
Unit
(Ta = 25°C
±
2°C , VSS = 0 V)
A/D Converter Performance
Limit
Parameter
Conversion relative error
A/D Conversion Time
Analog Input Voltage
Symbol
∆NLAD
tAD
fosc = 14.32 MHz
0
8
5
Condition
min
typ
max
±
3
LSB
µ
s
V
Unit
(Ta = 25°C
±
2°C , VDD = 5.0 V , VSS = 0 V)
104
MAD00028BEM
MN101D02D , MN101D02F , MN101D02G
MN101D02H
Pin Assignment
AFCLPF(↔PB2)
53
FSCLPF(↔PB0)
LCOSO(↔PA7)
LCOSI(↔PA6)
VOW1(↔PA0)
VOW2(↔PA1)
VOW3(↔PA2)
VOW4(↔PA3)
PGMM(←P92)
VOB1(↔PA4)
VOB2(↔PA5)
AFCC(↔PB3)
52
FSCI(↔PB1)
YPG(←P91)
YFG(PFG)
RCTLN
RCTLP
AVDD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
51
VDD2
CTLA
AVSS
VRO
AFG
FGF
VRI
CO
TPZ(→P90)
AD11(↔PC3)
AD10(↔PC2)
AD9(↔PC1)
AD8(↔PC0)
AD7(↔P87)
AD6(↔P86)
AD5(↔P85)
AD4(↔P84)
AD3(↔P83)
AD2(↔P82)
AD1(↔P81)
AD0(↔P80)
LED7(↔P77)
LED6(↔P76)
LED5(↔P75)
LED4(↔P74)
LED3(↔P73)
LED2(↔P72)
LED1(↔P71)
LED0(↔P70)
ROTA(↔P67)
HAMP(↔P66)
DENV(↔P65)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
50
49
48
47
46
45
44
43
42
41
CVIN2(PB4↔)
CVIN(PB5↔)
VSS2
CVOUT(PB6↔)
HSYNC(PB7↔)
VSYN(P20↔)
OSCO2(P21↔)
OSCI2(P22↔)
SXI
XO(P23↔)
XI(P24↔)
VSS
OSCI
OSCO
VDD
PWM14(P25↔)
PWM0
PWM1
SBUFD1(P11/PWM2↔)
SBUFD2(P12/PWM3↔)
SBUFD3(P13/FF15↔)
SBUFD4(P14/TC3O↔)
SBUFD5(P15/TC4I↔)
SBUFD6(OSDH/P16/XDSCK)
SBUFD7(OSDV/P17/OSCDIV/XDSDAT)
MN101D02D
MN101D02F
MN101D02G
MN101D02H
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
HSW
HBUFD2/DAOUT(P42↔)
HBUFD0(P40↔)
VLP
HBUFD6/BUZZER(P46↔)
KEYIRQ4(P54↔)
KEYIRQ3(P53↔)
KEYIRQ2(P52↔)
KEYIRQ1(P51↔)
KEYIRQ0(P50↔)
QFP100-P-1818B
*Pb
free
Support Tool
In-circuit Emulator
EPROM Built-in Type
PX-ICE101C / D + PX-PRB101D02-QFP100-P-1818B
Type
OTP: MN101DP02JAF [ES (Engineering Sample) available]
ATP: MN101DP02JAC [ES (Engineering Sample) available]
ROM (× 8-bit)
RAM (× 8-bit)
Minimum instruction execution time
192 K
5K
0.1397
µs
(at 4.0 V to 5.5 V, 14.32 MHz)
71.5
µs
(at 2.2 V to 5.5 V, fixed to 14.32 MHz internal division)
Package
OTP: QFP100-P-1818B
*Pb free
ATP: with ceramic window
HBUFD4(P44↔)
NSBT1(P07↔)
NSBI1(P06↔)
NSBO1(P05↔)
NSBT0(P02↔)
NSBI0(P01↔)
NSBO0(P00↔)
NRST(P04←)
SDA(P27↔)
IRQ0(P64→)
IRQ1(P63↔)
IRQ2(P62↔)
IRQ3(P61↔)
IRQ4(P60↔)
SCK(P26↔)
MAD00028BEM
105
PCB设计
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