K4J10324QD
1Gb GDDR3 SDRAM
1Gbit GDDR3 SDRAM
136FBGA with Halogen-Free & Lead-Free
(RoHS compliant)
Revision 1.2
May 2008
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev. 1.2 May 2008
K4J10324QD
Revision History
Revision
0.1
Month
Feb
Year
2007
Target Spec
• Power up sequence
• EMRS for 2CS mode
Preliminary Spec
• 3 kinds of ball out
- 1CS ball out for non-merged mode
- 2CS ball out for non-merged mode
- ball out for Merged mode
•
VDD/VDDQ power define.
- VDD/VDDQ : 1.9V + 0.1V of HJ1A(2Gbps)
- VDD/VDDQ : 1.8V + 0.1V of HC11/12/14
• tCDLR2 : BL/2-2
• Revised Vendor ID code
• Revised PKG code name
History
1Gb GDDR3 SDRAM
0.2
August
2007
0.3
October
2007
1.0
Feburary
2008
The first copy
• Change Vdd spec on page 3, page 52
• Add EMRS code for operating mode selection on page 19
• Add ICC values on page 54
• Change the package diagram as the standard FBGA format on page 58
Thermal characteristics on page 53
Remove 900MHz in ordering information on page 3.
Correction typo on page 19.(MRS set usage for CS mode and Merged mode table)
Adding tCKE parameter on page 57.(tCKE=5tCK)
1.1
1.2
Feburary
May
2008
2008
- 2 -
Rev. 1.2 May 2008
K4J10324QD
1Gb GDDR3 SDRAM
4M x 32Bit x 8 Banks Graphic Double Data Rate 3 Synchronous DRAM
with Uni-directional Data Strobe
FEATURES
• 1.7V(min) ~ 1.9V(max) power supply for device operation
• 1.7V(min) ~ 1.9V(max) power supply for I/O interface
• On-Die Termination (ODT)
• Output Driver Strength adjustment by EMRS
• Calibrated output drive
• 1.8V Pseudo Open drain compatible inputs/outputs
• Merged mode or non merged mode set by EMRS2.
• 1CS mode or 2CS mode set by EMRS1
• Fully independent 8banks are selected by CS0 and CS1
• Differential clock inputs (CK and CK)
• Commands entered on each positive CK edge
• CAS latency : 7, 8, 9, 10, 11, 12, 13 (clock)
• Programmable Burst length : 4 and 8
• Programmable Write latency : 1, 2, 3, 5, 6 and 7 (clock)
• Single ended READ strobe (RDQS) per byte
• Single ended WRITE strobe (WDQS) per byte
• RDQS edge-aligned with data for READs
• WDQS center-aligned with data for WRITEs
• Data Mask(DM) for masking WRITE data
• Auto & Self refresh modes
• Auto Precharge option
• 32ms, auto refresh (8K cycle)
• Halogen-free & Lead-free 136 Ball FBGA
• Maximum clock frequency up to 1GHz
• Maximum data rate up to 2.0Gbps/pin
• DLL for outputs
• Boundary scan function with SEN pin.
• Mirror function with MF pin
ORDERING INFORMATION
Part NO.
K4J10324QD-HJ1A*
K4J10324QD-HC12
K4J10324QD-HC14
Max Freq.
1000MHz
800MHz
700MHz
Max Data Rate
2.0Gbps/pin
1.6Gbps/pin
1.4Gbps/pin
VDD&VDDQ
1.85V+0.05V
1.8V+0.1V
136 Ball FBGA
Package
Note : * HJ1A should be selected high performence EMRS mode. And HJ1A hasn’t backward compatibility with HC12/HC14
and vice versa.
Refer to the EMRS2 code on the page 19.
GENERAL DESCRIPTION FOR 4M x 32Bit x 8 Bank GDDR3 SDRAM
The K4J10324QD is 1G bits of hyper synchronous data rate Dynamic RAM organized as 16 x 2,097,152 words by 32 bits, fabricated with
SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to
8.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, and programmable laten-
cies allow the device to be useful for a variety of high performance memory system applications.
32MX32 GDDR3 SGRAM ADDRESSING
CONFIGURATION
Row address
Column address
Bank address
Autoprecharge
Refresh
Refresh period
32MX32 GDDR3 Addressing Scheme
1CS mode(CS0)
A0~A12
A0~A7,A9
BA0~BA2
A8
8K/32ms
3.9us
2CS mode(CS0
/ CS1)
A0~A11
A0~A7,A9
BA0~BA2
A8
8K/32ms
3.9us
- 3 -
Rev. 1.2 May 2008
K4J10324QD
PIN CONFIGURATION
Normal Package (Top View)
1Gb GDDR3 SDRAM
1CS mode in Non-Merged Mode
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
V
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSS
VREF
VSSA
VDDA
VSS
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
2
VDD
DQ0
DQ2
WDQS0
DQ4
DQ6
VSSQ
A1
A12
A10
VSSQ
DQ24
DQ26
WDQS3
DQ28
DQ30
VDD
3
VSS
DQ1
DQ3
RDQS0
DM0
DQ5
DQ7
RAS
RFU
A2
DQ25
DQ27
DM3
RDQS3
DQ29
DQ31
VSS
4
ZQ
VSSQ
VDDQ
VSSQ
VDDQ
CAS
BA0
CKE
VDDQ
A0
A11
A3
VDDQ
VSSQ
VDDQ
VSSQ
SEN
5
6
7
8
9
MF
VSSQ
VDDQ
VSSQ
VDDQ
CS0
BA1
WE
VDDQ
A4
A7
A9
VDDQ
VSSQ
VDDQ
VSSQ
RESET
10
VSS
DQ9
DQ11
RDQS1
DM1
DQ13
DQ15
BA2
CK
A6
DQ17
DQ19
DM2
RDQS2
DQ21
DQ23
VSS
11
VDD
DQ8
DQ10
WDQS1
DQ12
DQ14
VSSQ
A5
CK
A8/AP
VSSQ
DQ16
DQ18
WDQS2
DQ20
DQ22
VDD
12
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSS
VREF
VSSA
VDDA
VSS
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
Note :
1. This ballout is for 1CS mode in Non-merged mode. This mode is a normal functionality mode for 1Gb GDDR3
2. 1CS mode use CS0 and A12 (don’t care J3 pin ) by EMRS1.
3. RFU is reserved for future use
- 4 -
Rev. 1.2 May 2008
K4J10324QD
PIN CONFIGURATION
Normal Package (Top View)
1Gb GDDR3 SDRAM
2CS mode in Non-Merged Mode
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
V
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSS
VREF
VSSA
VDDA
VSS
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
2
VDD
DQ0
DQ2
WDQS0
DQ4
DQ6
VSSQ
A1
RFU
A10
VSSQ
DQ24
DQ26
WDQS3
DQ28
DQ30
VDD
3
VSS
DQ1
DQ3
RDQS0
DM0
DQ5
DQ7
RAS
CS1
A2
DQ25
DQ27
DM3
RDQS3
DQ29
DQ31
VSS
4
ZQ
VSSQ
VDDQ
VSSQ
VDDQ
CAS
BA0
CKE
VDDQ
A0
A11
A3
VDDQ
VSSQ
VDDQ
VSSQ
SEN
5
6
7
8
9
MF
VSSQ
VDDQ
VSSQ
VDDQ
CS0
BA1
WE
VDDQ
A4
A7
A9
VDDQ
VSSQ
VDDQ
VSSQ
RESET
10
VSS
DQ9
DQ11
RDQS1
DM1
DQ13
DQ15
BA2
CK
A6
DQ17
DQ19
DM2
RDQS2
DQ21
DQ23
VSS
11
VDD
DQ8
DQ10
WDQS1
DQ12
DQ14
VSSQ
A5
CK
A8/AP
VSSQ
DQ16
DQ18
WDQS2
DQ20
DQ22
VDD
12
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
VSS
VREF
VSSA
VDDA
VSS
VDD
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
Note :
1. This ballout is for 2CS mode in Non-merged mode. This mode is a special mode for 1Gb GDDR3
2. 2CS mode use both CS0 and CS1 ( don’t care J2 pin ) by EMRS1.
3. RFU is reserved for future use.
- 5 -
Rev. 1.2 May 2008
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