Product Specification
PE4302
Product Description
The PE4302 is a high linearity, 6-bit RF Digital Step Attenuator
(DSA) covering a 31.5 dB attenuation range in 0.5 dB steps.
This 50-ohm RF DSA provides both parallel and serial CMOS
control interface operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4302 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4 mm QFN
footprint.
The PE4302 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
Switched Attenuator Array
RF Input
RF Output
50
Ω
RF Digital Attenuator
6-bit, 31.5 dB, DC – 4.0 GHz
Features
•
Attenuation: 0.5 dB steps to 31.5 dB
•
Flexible parallel and serial programming
interfaces
•
Unique power-up state selection
•
Positive CMOS control logic
•
High attenuation accuracy and linearity
over temperature and frequency
•
Very low power consumption
•
Single-supply operation
•
50
Ω
impedance
•
Packaged in a 20 lead 4x4mm QFN
Figure 2. Package Type
4x4 mm 20-Lead QFN
Parallel Control
Serial Control
Power-Up Control
6
3
Control Logic Interface
2
Table 1. Electrical Specifications @ +25°C, V
DD
= 3.0 V
Parameter
Operation Frequency
Insertion Loss
2
Attenuation Accuracy
1 dB Compression
3
Input IP3
1,2
Return Loss
Switching Speed
50% control to 0.5 dB
of final value
Two-tone inputs
+18 dBm
Any Bit or Bit
Combination
DC - 2.2 GHz
DC
≤
1.0 GHz
1.0 < 2.2 GHz
1 MHz - 2.2 GHz
1 MHz - 2.2 GHz
DC - 2.2 GHz
Test Conditions
Frequency
Minimum
DC
-
-
30
-
15
-
Typical
Maximum
4000
Units
MHz
dB
dB
dB
dBm
dBm
dB
µs
1.5
-
34
52
20
-
1.75
±(0.10 + 3% of atten setting)
±(0.15 + 5% of atten setting)
-
-
-
1
Notes: 1. Device Linearity will begin to degrade below 1 Mhz
2. See Max input rating in Table 3 & Figures on Pages 2 to 4 for data across frequency.
3. Note Absolute Maximum in Table 3.
Document No. 70-0056-04
│
www.psemi.com
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE4302
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0 V
Figure 3. Insertion Loss
Figure 4. Attenuation at Major steps
0
35
31.5dB
-1
30
25
Insertion Loss (dB)
-40C
25C
-3
85C
Normalized to Insertion Loss
Attenuation (dB)
-2
20
16dB
15
2dB
10
8dB
4dB
1dB
0.5dB
-4
-5
5
0
-6
0
500
1000
1500
2000
2500
3000
3500
4000
0
500
1000
1500
2000
2500
3000
3500
4000
RF Frequency (MHz)
RF Frequency (MHz)
Figure 5. Input Return Loss at Major
Attenuation Steps
0
Figure 6. Output Return Loss at Major
Attenuation Steps
0
-10
-10
-20
S11 (dB)
S22 (dB)
-20
-30
16dB
-30
31.5dB
-40
31.5dB
-40
-50
0
500
1000
1500
2000
2500
3000
3500
4000
-50
0
500
1000
1500
2000
2500
3000
3500
4000
RF Frequency (MHz)
RF Frequency (MHz)
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
Document No. 70-0056-04
│
UltraCMOS™ RFIC Solutions
PE4302
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0 V
Figure 7. Attenuation Error Vs. Frequency
Figure 8. Attenuation Error Vs. Attenuation
Setting
0.5
2
0
31.5 (dB)
0
Attenuation Error (dB)
10Mhz
500Mhz
1000Mhz
-0.5
1500Mhz
2000Mhz
-1
-8
2200Mhz
Attenuation Error (dB)
-2
-4
-6
-10
0
500
1000
1500
2000
2500
3000
3500
4000
-1.5
0
5
10
15
20
25
30
35
40
RF Frequency (MHz)
Attenuation Setting (dB)
Figure 9. Attenuation Error Vs. Attenuation
Setting
0.6
Figure 10. Attenuation Error Vs. Attenuation
Setting
0.4
0.4
0.2
0
1000Mhz, -40C
-0.2
1000Mhz, 25C
1500Mhz, -40C
-0.6
10Mhz, 85C
1000Mhz, 85C
1490Mhz, 25C
1490Mhz, 85C
Attenuation Error (dB)
0.2
500Mhz, -40C
0
10Mhz, 25C
-0.2
500Mhz, 25C
Attenuation Error (dB)
10Mhz, -40C
-0.4
-0.4
500Mhz, 85C
-0.8
-1
-0.6
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Attenuation Setting (dB)
Attenuation Setting (dB)
Note: Positive attenuation error indicates higher attenuation than target value
Document No. 70-0056-04
│
www.psemi.com
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE4302
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0 V
Figure 11. Attenuation Error Vs. Frequency
Figure 12. Input IP3 Vs. Frequency
0.5
2200Mhz, -40C
60
55
50
2000Mhz, -40C
Input IP3 (dBm)
45
40
35
30
2000Mhz, 85C
25
.5dB
2dB
8dB
31.5dB
0dB
1dB
4dB
16dB
0
Attenuation Error (dB)
-0.5
2200Mhz, 25C
2000Mhz, 25C
2200Mhz, 85C
-1
-1.5
0
5
10
15
20
25
30
35
40
20
0
500
1000
1500
2000
2500
3000
Attenuation Setting (dB)
RF Frequency (MHz)
Figure 13. Input 1 dB Compression
40
35
1dB Compression (dBm)
30
25
20
0dB
15
0.5dB
10
0
500
1000
1500
2000
2500
3000
2dB
8dB
31.5dB
1dB
4dB
16dB
RF Frequency (MHz)
Note: Positive attenuation error indicates higher attenuation than target value
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
Document No. 70-0056-04
│
UltraCMOS™ RFIC Solutions
PE4302
Product Specification
Figure 14. Pin Configuration (Top View)
GND
C0.5
C1
C2
C4
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
Parameter/Conditions
Power supply voltage
Voltage on any DC input
Storage temperature range
Input power (50Ω)
ESD voltage (Human Body
Model)
Min
-0.3
-0.3
-65
Max
4.0
V
DD
+
0.3
150
+30
500
Units
V
V
°C
dBm
V
20
19
18
17
C16
RF1
Data
Clock
LE
16
1
2
3
4
5
10
15
C8
RF2
P/S
Vss/GND
GND
T
ST
P
IN
V
ESD
20-lead QFN
4x4mm
Exposed Solder Pad
14
13
12
11
V
DD
V
DD
PUP1
PUP2
GND
Exceeding absolute maximum ratings may cause per-
manent damage. Operation should be restricted to the
limits in the Operating Ranges table. Operation be-
tween operating range maximum and absolute maxi-
mum for extended periods may reduce reliability.
6
7
8
9
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Paddle
Table 4. Operating Ranges
Parameter
Description
Min
2.7
Pin
Name
C16
RF1
Data
Clock
LE
V
DD
PUP1
PUP2
V
DD
GND
GND
V
ss
/GND
P/S
RF2
C8
C4
C2
GND
C1
C0.5
GND
Typ
3.0
Max
3.3
100
Units
V
µA
V
Attenuation control bit, 16dB (Note 4).
RF port (Note 1).
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
Power-up selection bit, MSB.
Power-up selection bit, LSB.
Power supply pin.
Ground connection.
Ground connection.
Negative supply voltage or GND
connection(Note 3)
Parallel/Serial mode select.
RF port (Note 1).
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Attenuation control bit, 1 dB.
Attenuation control bit, 0.5 dB.
Ground for proper operation
V
DD
Power Supply
Voltage
I
DD
Power Supply
Current
Digital Input High
Digital Input Low
Digital Input Leakage
Input Power
Temperature range
0.7xV
DD
0.3xV
DD
1
+24
-40
85
V
µA
dBm
°C
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™ de-
vices are immune to latch-up.
Switching Frequency
The PE4302 has a maximum 25 kHz switching rate.
Resistor on Pin 1 & 3
A 10 kΩ resistor on the inputs to Pin 1 & 3 (see Figure
16) will eliminate package resonance between the RF
input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
Note 1: Both RF ports must be held at 0 V
DC
or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 kΩresistor to V
DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V
SS
(-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 kΩresistor in series, as close to pin as possible to
avoid frequency resonance.
Document No. 70-0056-04
│
www.psemi.com
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
