SED1330
CMOS GRAPHIC LCD CONTROLLER
This part is replaced by SED1335. Some pin differences between SED1330 and SED1335 exist. Please check
SED1335 data sheet. S-MOS Systems, Inc., will continue to support existing designs which use SED1330.
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DESCRIPTION
The SED1330 is a CMOS low-power dot matrix liquid crystal graphic display controller. The device stores in
external RAM display data sent by an 8-bit microcomputer, and generates all the signals required by the LCD
drivers. The LSI incorporates an internal character generator ROM which supports user-defined characters
(also an external CGROM can be supported).
The SED1330 can be interfaced to high-speed microprocessors such as the Intel family or Motorola family.
The controller supports a set of rich commands that will allow the user to create a layered display of characters
and graphics.
Also, the controller functions as a pipeline buffer between the MPU and display memory so that low-cost,
medium-speed SRAM can be used.
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FEATURES
•
CMOS low-power graphic and character display
controller
interface is compatible
•
Selectable MPUand the Motorola family with both
the Intel family
•
Smooth scrolling support:
•
•
Horizontal and vertical scroll
Scrolling of selected areas of the display
Multimode display:
2 layers of overlapping character and graphics
3 layers of overlapping graphics
Selectable display synthesis:
Inverse video
Flashing display, cursor on/off/blink
Under and bar cursor, block cursor
Simple animation
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SYSTEM BLOCK DIAGRAM
•
Programmable cursor
•
Internal character generator ROM
•
Supports external character generator ROM:
•
8
×
8 or 8
×
16 pixel characters
Allows mixing of ROM and RAM character sets
Supports 64K bytes of memory:
2 of 32K
×
8 100ns SRAM
or 8 of 8K
×
8 100ns SRAM
Display duty .................................. 1/2 to 1/256
•
................ 5mA
•
Low power dissipation0.05µA (typical), (typical)
standby
•
Logic power supply ........................ 4.5 to 5.5V
Plastic QFP5-60 pin (FBA)
•
Package ................ Plastic QFP6-60 pin (FBB)
DATA
CPU
68xx
80xx
CONTROL
SED1330F
LCD
SRAM
125
SED1330
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PIN DESCRIPTIONS
Pin Name
XG
XD
V
DD
V
SS
SEL1, 2
D0 to D7
A0
RD
WR
CS
RES
VA0 to VA15
VD0 to VD7
VR/W
VCE
XD0 to XD3
XSCL
XECL
LP
WF
YSCL
YD
YDIS
Pin No.
SED1330F
BA
54
55
58
13
53 • 52
59 to 60
1 to 6
57
50
51
56
47
43 to 30
28 to 27
26 to 19
44
45
10 to 7
12
11
14
15
18
17
16
SED1330F
BB
17
18
21
36
16 • 15
22 to 29
20
13
14
19
10
6 to 1
59 to 50
49 to 42
7
8
33 to 30
35
34
37
38
41
40
39
I/O
I
O
+5V
GND (0V)
I
I/O
I
I
I
I
I
O
I/O
O
O
O
O
O
O
O
O
O
O
Functions
Oscillator terminal
Oscillator terminal
Power supply
Power supply
MPU interface format selection
Data bus
Data type selection
80 series Read strobe signal
68 series “E” clock
80 series Write strobe signal
68 series R/W signal
Chip select
Reset
VRAM address bus
VRAM data bus
VRAM R/W signal
Memory control signal
Dot data output bus to X driver
Dot data shift clock for X driver
Chip enable shift clock for Y driver
Dot data latch pulse
Frame signal
Scan data shift clock for Y driver
Scan data output
Power down signal when display OFF
NC: No Connection
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
•
(V
SS
= 0V)
Symbol
V
DD
V
I
P
D
T
opr
T
stg
T
sol
Ratings
–0.3 to 7.0
–0.5 to V
DD
+0.5
300
–20 to 75
–60 to 150
260°C, 10s (at lead)
Unit
V
V
mW
°C
°C
—
Parameter
Supply voltage
Input voltage
Power dissipation
Operating temperature
Storage temperature
Soldering temperature and time
127
SED1330
•
DC ELECTRICAL CHARACTERISTICS
Parameter
Operating voltage
Register data retention voltage
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Positive trigger threshold voltage
Negative trigger threshold voltage
Symbol
V
DD
V
OH
V
IHT
V
ILT
V
OHT
V
OLT
V
IHC
V
ILC
V
OHC
V
OLC
V
T+
V
T–
I
LI
I
LO
I
DDA
I
DDS
f
OSC
f
CLK
R
f
(V
DD
= 5V±10%, V
SS
= 0V, T
a
= –20 to 75°C)
Condition
Min
4.5
2.0
D0 to D7, A0, CS, RD, WR,
VD0 to VD7, I
OH
= –5.0mA,
I
OL
=5.0mA, VR/W, VCE,
REF
I
OH
=1.6mA, I
OL
= –1.6mA,
SEL1, 2, SYNC, YD, XD0 to
YSCL, YDIS, OSC1, OSC2
RES *
V
I
=V
DD
or V
SS
f
OSC
=10MHz, No load
(No external V-RAM)
XG=CS=V
DD
Typ
5.0
—
—
—
—
—
—
—
—
—
Max
5.5
6.0
V
DD
+0.3
0.8
—
0.4
—
0.2V
DD
—
0.4
Unit
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
mA
µA
MHz
MHz
MΩ
T
T
L
C
M
O
S
SCHMITT
2.2
–0.3
2.4
—
0.8V
DD
—
—
XD3, XSCL, XECL, LP, FR, V
DD
–0.4
0.5V
DD
0.7V
DD
0.8V
DD
0.2V
DD
0.3V
DD
0.5V
DD
—
—
—
—
1.0
—
0.5
0.05
0.10
8
0.05
—
—
1.0
2.0
5.0
12
20
10.0
10.0
5.0
Input leakage current
Output leakage current
Average operating current
Standby current
Oscillation frequency
External clock frequency
Feed back resistance
AT X’tal
XG, XD
* RES input pulse should be longer than 1.0ms.
VL5 should be OFF when RES is “L”.
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