MCP3901
Two-Channel Analog Front End
Features
• Two Synchronous Sampling 16/24-bit Resolution
Delta-Sigma A/D Converters with Proprietary
Multi-Bit Architecture
• 91 dB SINAD, -104 dBc Total Harmonic Distortion
(THD) (up to 35
th
harmonic), 109 dB Spurious-free
Dynamic Range (SFDR) for Each Channel
• Programmable Data Rate up to 64 ksps
• Ultra Low-Power Shutdown mode with <2 µA
• -133 dB Crosstalk Between the Two Channels
• Low Drift Internal Voltage Reference: 12 ppm/°C
• Differential Voltage Reference Input Pins
• High Gain PGA on Each Channel (up to 32 V/V)
• Phase Delay Compensation Between the Two
Channels with 1 µs time Resolution
• Separate Modulator Outputs for Each Channel
• High-Speed, Addressable 20 MHz SPI Interface
with Mode 0,0 and 1,1 Compatibility
• Independent Analog and Digital Power Supplies:
4.5V-5.5V AV
DD
, 2.7V-5.5V DV
DD
• Low-Power Consumption: (14 mW typical at 5V)
• Available in Small 20-lead SSOP and QFN
Packages
• Industrial Temperature Ranges:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Description
The MCP3901 is a dual channel Analog Front End
(AFE) containing two synchronous sampling Delta-
Sigma Analog-to-Digital Converters (ADC), two PGAs,
phase delay compensation block internal voltage
reference, modulator output block, and high-speed
20 MHz SPI compatible serial interface. The converters
contain a proprietary dithering algorithm for reduced
Idle tones and improved THD.
The internal register map contains 24-bit wide ADC
data words, a modulator output byte, as well as six
writable control registers to program gain,
oversampling ratio, phase, resolution, dithering,
shutdown, Reset and several communication features.
The communication is largely simplified with various
Continuous Read modes that can be accessed by the
Direct Memory Access (DMA) of an MCU and with a
separate data ready pin that can be connected directly
to an Interrupt Request (IRQ) input of an MCU.
The MCP3901 is capable of interfacing to a large
variety of voltage and current sensors, including
shunts, current transformers, Rogowski coils and Hall-
effect sensors.
Package Type
20-Lead SSOP
RESET
DV
DD
AV
DD
CH0+
CH0-
CH1-
CH1+
AGND
REFIN/OUT+
REFIN-
AV
DD
1
2
3
4
5
6
7
8
9
10
DV
DD
20
19
18
17
16
15
14
13
12
11
RESET
SDI
SDO
SCK
CS
OSC2
OSC1/CLKI
DR
MDAT0
MDAT1
DGND
SDO
Applications
•
•
•
•
Energy Metering and Power Measurement
Automotive
Portable Instrumentation
Medical and Power Monitoring
20 19 18 17 16
CH0+
CH0-
CH1-
CH1+
AGND
SDI
MDAT1
20-Lead QFN
1
2
3
4
5
6
REFIN/OUT+
15
SCK
EP
21
14
CS
13
OSC2
12
OSC1/CLKI
11
DR
7
REFIN-
8
DGND
9 10
MDAT0
* Includes Exposed Thermal Pad (EP); see
Table 3-1.
©
2011 Microchip Technology Inc.
DS22192D-page 1
MCP3901
Functional Block Diagram
AV
DD
Voltage
VREFEXT
Reference
+
V
REF
-
V
REF
- V
REF
+ ANALOG DIGITAL
SINC
3
CH0+
CH0-
+
-
PGA
Δ
-Σ
Modulator
Φ
CH1+
CH1-
+
-
PGA
Δ
-Σ
Modulator
SINC
3
MODOUT<1:0>
Modulator
Output Block
DATA_CH0<23:0>
DR
SDO
Phase
Shifter
PHASE <7:0>
Digital SPI
Interface
RESET
SDI
SCK
CS
DV
DD
AMCLK
DMCLK/DRCLK
Clock
Generation
Xtal Oscillator
OSC1
MCLK
OSC2
REFIN/OUT+
REFIN -
DMCLK
OSR<1:0>
PRE<1:0>
DATA_CH1<23:0>
DUAL DS ADC
SDN<1:0>, RESET<1:0>, GAIN<7:0>
POR
AV
DD
Monitoring
AGND
MOD<7:0>
POR
DGND
MDAT0
MDAT1
DS22192D-page 2
©
2011 Microchip Technology Inc.
MCP3901
1.0
ELECTRICAL
CHARACTERISTICS
† Notice:
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions, above those indi-
cated in the operational listings of this specification, is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Absolute Maximum Ratings †
V
DD
...................................................................................7.0V
Digital inputs and outputs w.r.t. A
GND
........ -0.6V to V
DD
+0.6V
Analog input w.r.t. A
GND
..................................... ....-6V to +6V
V
REF
input w.r.t. A
GND
............................... -0.6V to V
DD
+0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD on the analog inputs (HBM,MM) ................. 7.0 kV, 400V
ESD on all other pins (HBM,MM) ........................ 7.0 kV, 400V
ELECTRICAL CHARACTERISTICS
Electrical Specifications:
Unless otherwise indicated, AV
DD
= 4.5 to 5.5V, DV
DD
= 2.7 to 5.5V; -40°C < T
A
< +85°C,
MCLK = 4 MHz; PRESCALE =
1;
OSR = 64; GAIN =
1;
Dithering OFF; V
IN
= -0.5 dBFS = 333 mV
RMS
@ 50/60 Hz
Parameters
Internal Voltage Reference
Internal Voltage Reference
Tolerance
Temperature Coefficient
Output Impedance
Voltage Reference Input
Input Capacitance
Differential Input Voltage Range
(V
REF+
– V
REF-
)
Absolute Voltage on REFIN+ Pin
Absolute Voltage on REFIN- Pin
ADC Performance
Resolution (No Missing Codes)
Sampling Frequency
Note 1:
f
S
24
—
See
Table 4-2
—
bits
kHz
OSR = 256
(See
Table 5-3)
f
S
= DMCLK = MCLK/
(4 x PRESCALE)
V
REF
V
REF+
V
REF-
—
2.2
1.9
-0.3
—
—
—
—
10
2.6
2.9
0.3
pF
V
V
V
V
REF
= (V
REF+
– V
REF-
),
VREFEXT =
1
VREFEXT =
1
V
REF
TC
REF
ZOUT
REF
-2%
—
—
2.37
12
7
+2%
—
—
V
VREFEXT =
0
Symbol
Min
Typical
Max
Units
Conditions
ppm/°C VREFEXT =
0
kΩ
AV
DD
= 5V,
VREFEXT =
0
2:
3:
4:
5:
6:
7:
8:
This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic performance is specified at -0.5 dB below the
maximum signal range, V
IN
= -0.5 dBFS @ 50/60 Hz = 353 mV
RMS,
V
REF
= 2.4V.
See terminology section for definition.
This parameter is established by characterization and not 100% tested.
For these operating currents, the following bit settings apply: SHUTDOWN<1:0> =
00,
RESET<1:0> =
00,
VREFEXT =
0,
CLKEXT =
0.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN<1:0> =
11,
VREFEXT =
1,
CLKEXT =
1.
Applies to all gains. Offset error is dependant on PGA gain setting (see
Figure 2-19
for typical values).
Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied
continuously to the part with no risk for damage.
For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with
BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz,
AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to ‘0’.
©
2011 Microchip Technology Inc.
DS22192D-page 3
MCP3901
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications:
Unless otherwise indicated, AV
DD
= 4.5 to 5.5V, DV
DD
= 2.7 to 5.5V; -40°C < T
A
< +85°C,
MCLK = 4 MHz; PRESCALE =
1;
OSR = 64; GAIN =
1;
Dithering OFF; V
IN
= -0.5 dBFS = 333 mV
RMS
@ 50/60 Hz
Parameters
Output Data Rate
Symbol
f
D
Min
Typical
See
Table 4-2
Max
Units
ksps
Conditions
f
D
= DRCLK = DMCLK/
OSR = MCLK/
(4 x PRESCALE x OSR)
All analog input
channels, measured to
AGND
(Note
7)
(Note
4)
-40°C < T
A
< 125°C
(Note
1)
(Note
6)
From -40°C to +125°C
G=
1
All Gains
GAIN =
1,
DITHER = On
Proportional to
1/AMCLK
OSR = 256,
DITHER = On
OSR = 256,
DITHER = On
OSR = 256,
DITHER = On
OSR = 256,
DITHER = On
OSR = 256,
DITHER = On
Analog Input Absolute Voltage
on CH0+, CH0-, CH1+,
CH1- Pins
Analog Input Leakage Current
CHn+
-1
—
+1
V
A
IN
—
—
—
-3
—
—
-2.5
—
1
2
—
—
3
-0.4
—
1
15
—
91
79
-104
-85
91
81
109
87
-133
—
—
500/GAIN
+3
—
—
+2.5
—
—
—
—
—
-102
-84
—
—
—
—
—
nA
nA
mV
mV
µV/°C
%
%
ppm
kΩ
dB
dB
dB
dB
dB
dB
dB
dB
dB
Differential Input Voltage Range (CHn+ – CHn-)
Offset Error
(Note
2)
Offset Error Drift
Gain Error
(Note
2)
Gain Error Drift
Integral Nonlinearity
(Note
2)
Input Impedance
Signal-to-Noise and Distortion
Ratio
(Notes
2, 3)
Total Harmonic Distortion
(Notes
2, 3)
Signal-to-Noise Ratio
(Notes
2, 3)
Spurious Free Dynamic Range
(Note
2)
Crosstalk (50/60 Hz)
(Note
2)
Note 1:
INL
Z
IN
SINAD
GE
V
OS
ppm/°C From -40°C to +125°C
—
350
89
78
THD
—
—
SNR
89
80
SFDR
—
—
CTALK
—
2:
3:
4:
5:
6:
7:
8:
This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic performance is specified at -0.5 dB below the
maximum signal range, V
IN
= -0.5 dBFS @ 50/60 Hz = 353 mV
RMS,
V
REF
= 2.4V.
See terminology section for definition.
This parameter is established by characterization and not 100% tested.
For these operating currents, the following bit settings apply: SHUTDOWN<1:0> =
00,
RESET<1:0> =
00,
VREFEXT =
0,
CLKEXT =
0.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN<1:0> =
11,
VREFEXT =
1,
CLKEXT =
1.
Applies to all gains. Offset error is dependant on PGA gain setting (see
Figure 2-19
for typical values).
Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied
continuously to the part with no risk for damage.
For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with
BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz,
AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to ‘0’.
DS22192D-page 4
©
2011 Microchip Technology Inc.
MCP3901
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications:
Unless otherwise indicated, AV
DD
= 4.5 to 5.5V, DV
DD
= 2.7 to 5.5V; -40°C < T
A
< +85°C,
MCLK = 4 MHz; PRESCALE =
1;
OSR = 64; GAIN =
1;
Dithering OFF; V
IN
= -0.5 dBFS = 333 mV
RMS
@ 50/60 Hz
Parameters
AC Power Supply Rejection
DC Power Supply Rejection
DC Common-Mode Rejection
Ratio
(Note
2)
Oscillator Input
Master Clock Frequency Range
Power Specifications
Operating Voltage, Analog
Operating Voltage, Digital
Power On Reset Threshold
AV
DD
DV
DD
POR
4.5
2.7
—
—
Operating Current, Analog
(Note
4)
AI
DD
—
—
—
—
Operating Current, Digital
DI
DD
—
—
—
Shutdown Current, Analog
Shutdown Current, Digital
Note 1:
I
DDS,A
I
DDS,D
—
—
—
3.6
4.2
4.6
2.1
2.1
3.8
3.8
0.45
0.25
1.2
—
—
5.5
5.5
—
—
2.8
3.3
5.6
7
1.0
0.45
1.6
1
1
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
(Note
3)
-40°C < T
A
< 125°C,
(Note
3)
BOOST<1:0> =
00
-40°C < T
A
< 125°C,
BOOST<1:0> =
00
BOOST<1:0> =
11
-40°C < T
A
< 125°C,
BOOST<1:0> =
11
DV
DD
= 5V,
MCLK = 4 MHz
DV
DD
= 2.7V,
MCLK = 4 MHz
DV
DD
= 5V,
MCLK = 8.192 MHz
AV
DD
pin only
(Note
5)
DV
DD
pin only
(Note
5)
MCLK
1
—
16.384
MHz
(Note
8)
Symbol
AC PSRR
DC PSRR
CMRR
Min
—
—
—
Typical
-77
-77
-72
Max
—
—
—
Units
dB
dB
dB
Conditions
AV
DD
and DV
DD
= 5V +
1 V
PP
@ 50/60 Hz
AV
DD
and DV
DD
= 4.5 to
5.5V
V
CM
varies from -1V to
+1V
2:
3:
4:
5:
6:
7:
8:
This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic performance is specified at -0.5 dB below the
maximum signal range, V
IN
= -0.5 dBFS @ 50/60 Hz = 353 mV
RMS,
V
REF
= 2.4V.
See terminology section for definition.
This parameter is established by characterization and not 100% tested.
For these operating currents, the following bit settings apply: SHUTDOWN<1:0> =
00,
RESET<1:0> =
00,
VREFEXT =
0,
CLKEXT =
0.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN<1:0> =
11,
VREFEXT =
1,
CLKEXT =
1.
Applies to all gains. Offset error is dependant on PGA gain setting (see
Figure 2-19
for typical values).
Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied
continuously to the part with no risk for damage.
For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with
BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz,
AMCLK = MCLK/PRESCALE. When using a crystal, the CLKEXT bit should be equal to ‘0’.
©
2011 Microchip Technology Inc.
DS22192D-page 5
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