TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
Issue 4.0 : March 1998
NE29 8SE, England Tel. +44 (0)191 2930500 Fax. +44 (0) 191
2590997
Description
A version 'A' with four independent write enables
The PUMA 68F16001 is a 16Mbit CMOS FLASH
(WE1-4) is available.
hmp
512K x 32 FLASH MODULE
PUMA 68F16001/A-12/15/20/25
memory module organised as 512K x 32 in a
JEDEC 68 pin surface mount PLCC, available with
access times of 120, 150, 200 and 250ns. The
output width is user configurable as 8 , 16 or 32 bits
using four Chip Selects (CS1~4).
Page write (256 Bytes) is performed in 10ms with
Toggle bit and DATA polling indication of cycle
completion. The device features both hardware
and software data protection and a low power
standby of 6.6mW. Write cycle endurance is
10,000 Erase/Write cycles with a data retention
time of 10 years.
Features
• Access Times of 120, 150, 200 and 250ns.
• JEDEC 68 'J' leaded plastic Surface Mount
Substrate.
• Industrial or Military.
• User Configurable as 8 / 16 / 32 bit wide
output.
• Operating Power :
880 mW (max)
• Standby Power : -L Part (
CMOS
)
6.6 mW (max)
• Page Write (256 Bytes) in 10ms typ.
• DATA Polling and Toggle bit indication of end of
write.
• Hardware and Software Data Protection.
• Endurance of 10
4
Erase/write Cycles and Data
Retention Time of 10 years.
Block Diagram (See page 10 for 'A' version)
Pin Definition (See page 10 for 'A' version)
NC
A0
A1
A2
A3
A4
A5
CS3
GND
CS4
WE
A6
A7
A8
A9
A10
Vcc
A0~A18
OE
WE
512K x 8
FLASH
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
512K x 8
FLASH
512K x 8
FLASH
512K x 8
FLASH
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
VIEW
17
53
FROM
18
52
19
51
ABOVE
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PUMA 68F16001
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
Vcc
A11
A12
A13
A14
A15
A16
CS1
OE
CS2
A17
NC
NC
NC
Pin Functions
A0~18
CS1~4
WE
V
CC
Address Inputs
Chip Select
Write Enable
Power (+5V)
D0~31
OE
NC
GND
Data Inputs/Outputs
Output Enable
No Connect
Ground
A18
GND
NC
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Operating Temperature
Storage Temperature
Input voltages (including N.C. pins) with Respect to GND
Output voltages with respect to GND
T
OPR
T
STG
V
IN
V
OUT
-55 to +125
-65 to +150
-0.6 to +6.25
-0.6 to V
CC
+0.6
°
C
°
C
V
V
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operating Conditions
min
DC Power Supply Voltage
Input Low Voltage
Input High Voltage
Operating Temp Range
V
CC
V
IL
V
IH
T
A
T
AI
T
AM
4.5
-
2.0
0
-40
-55
typ
5.0
-
-
-
-
-
max
5.5
0.8
-
70
85
125
V
V
V
°
C
°
C (I Suffix)
°
C (M Suffix)
DC Electrical Characteristics
(T
A
=-55°C to +125°C,V
CC
=5V ± 10%)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Symbol
I
LI1
32 bit I
LO
32 bit I
CC32
16 bit I
CC16
8 bit I
CC8
Test Condition
min
-
-
-
-
-
-
-
-
2.4
max
40
40
160
86
49
12
1.2
0.45
-
Unit
µA
µA
mA
mA
mA
mA
mA
V
V
V
IN
= GND to V
CC
V
IN
= GND to V
CC
, CS
(1)
=V
IH
CS
(1)
=OE=V
IL
, WE=V
IH
, I
OUT
=0mA, ƒ=5MHz
As above
As above
CS
(1)
= V
IH
, I
I/O
= 0mA, Other Inputs = V
IH
CS
(1)
= V
CC
-0.3V, I
I/O
= 0mA, Other Inputs = V
CC
I
OL
= 2.1mA.
I
OH
= -400µA.
Standby Supply Current TTL levels I
SB1
CMOS levels I
SB2
Output Low Voltage
Output High Voltage
V
OL
V
OH
Notes (1) CS above are accessed through CS1-4. These inputs must be operated simultaneously for 32 bit operation, in pairs
in 16 bit mode and singly for 8 bit mode.
Capacitance
(T
A
=25°C,ƒ=1MHz)
Note: These parameters are calculated, not measured.
Parameter
Input Capacitance
Output Capacitance
A0-A18, OE, WE
Other Inputs
Symbol
C
IN1
C
IN2
C
OUT
Test Condition
V
IN
=0V
V
IN
=0V
V
OUT
=0V
typ
-
-
-
max Unit
30
10
52
pF
pF
pF
2
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
AC OPERATING CONDITIONS
Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable Access Time
Chip Select High to High Z Output
Output Enable High to High Z Output
Output Hold from Address Change
(2) All parameter Units are nS
Write Cycle
Parameter
Write Cycle Time
Address Set-up Time
Address Hold Time
Output Enable Set-up Time
Output Enable Hold Time
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width
Write Enable High Recovery
Data Set-up Time
Data Hold Time
Byte Load Cycle
Symbol
t
WC
t
AS
t
AH
t
OES
t
OEH
t
CS
t
CH
t
WP
t
WPH
t
DS
t
DH
t
BLC
min
-
10
50
10
10
0
0
90
100
50
10
-
typ
-
-
-
-
-
-
-
-
-
-
-
-
max
10
-
-
-
-
-
-
-
-
-
-
150
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Symbol
t
RC
t
AA
t
CS
t
OE
t
HZ
t
OHZ
t
OH
-12
min max
120
-
-
0
0
0
0
-
120
120
50
30
30
-
-15
min max
150
-
-
0
0
0
0
-
150
150
70
40
40
-
-20
min max
200
-
-
0
0
0
0
-
200
200
80
50
50
-
-25
min max
250
-
-
0
0
0
0
-
250
250
90
60 (1)
60 (1)
-
Notes:(1) t
HZ
is specified from OE or CS 1-4 whichever occurs first (Cl=5 pf).
AC Test Conditions
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: 1 TTL gate + 100pF
* V
CC
=5V±10%
Output Test Load
I/O Pin
645
Ω
1.76V
100pF
3
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
AC Write Waveform - WE Controlled
OE
t
OES
t
OEH
ADDRESS
CE
WE
t
AS
t
CS
t
WPH
t
WP
DATA
IN
t
DS
t
DH
t
AH
t
CH
AC Write Waveform - CS Controlled
OE
t
OES
t
OEH
ADDRESS
t
AS
t
AH
t
CH
CE
WE
t
CS
t
WPH
t
WP
t
DS
t
DH
DATA
IN
4
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
Read Cycle Timing Waveform
Address
Address Valid
t
RC
t
CS
CS
t
OE
t
OLZ
t
OHZ
OE
t
LZ
t
OH
HIGH z
t
HZ
Dout
Output
Valid
t
AA
Output
Valid
Software Protected Write Waveform
OE
CE
t
WP
t
BLC
WE
t
AS
t
AH
t
WPH
BYTE ADDRESS
A0~A7
5555
2AAA
5555
A8~A18
t
DS
t
DH
PAGE ADDRESS
t
WC
A0
Byte 0
Byte 254
Byte 255
Data
AA
55
Note: (1) A8 through A18 must specify the page address during each high to low transition of Write Enable (or Chip select).
(2) Output Enable must be high only when Write Enable and Chip Select are both low.
(3) All bytes that are not loaded within the sector being programmed will be indeterminate.
5
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