DATA BULLETIN
MX604
FEATURES
1200bps forward, 75bps back channels
Conforms to relevant sections of v.23
and ETSI specifications
Line Equalization
1200bps Data Retiming Facility can
eliminate external UART
Low Voltage Operation (3.3 to 5.0V)
v.23 Compatible Modem
PRELIMINARY INFORMATION
APPLICATIONS
Low Power Operation
1mA typ. @ 3.3V Operating Mode
1A typ. Zero-Power Mode
Standard 3.58Mhz Xtal/Clock
Telephone Telemetry System
Applications
Status
Telephone
Line
Line
Interface
Control
MX604
Data
µC
The MX604 is a low voltage, low power CMOS device, used for the reception or transmission of asynchronous
1200bps data and full-duplex 75bps back channel data in accordance with CCITT V.23 and ETSI
specifications.
This device provides an optional Tx and Rx data retiming function which can eliminate, based on user
preference, the need for an external UART when operating at 1200bps. The device can disable the back
channel or be operated so only the mark or space tone is produced. The optional line equalizer is
incorporated into the receive path and is controlled by an external logic level.
The MX604 may be used in a wide range of telephone telemetry systems. Low voltage capability, a low
operating current (1mA typ. @ V
DD
= 3.3V), and a very low current 'sleep' mode (1A typ.) make the MX604
ideal for both portable terminal and line powered applications.
The MX604 is available in the following packages: 24-pin TSSOP (MX604TN), 16-pin SOIC (MX604DW) and
16-pin PDIP (MX604P).
1998
MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
2
MX604 PRELIMINARY INFORMATION
CONTENTS
Section
1.
2.
3.
4.
Page
Block Diagram .......................................................................................................... 3
Signal List ................................................................................................................. 4
External Components .............................................................................................. 5
General Description ................................................................................................. 5
4.1 Xtal Osc and Clock Dividers ................................................................................................... 5
4.2 Mode Control Logic ................................................................................................................ 6
4.3 Rx Input Amplifier ................................................................................................................... 6
4.4 Receive Filter and Equalizer................................................................................................... 6
4.5 Energy Detector...................................................................................................................... 7
4.6 FSK Demodulator ................................................................................................................... 7
4.7 FSK Modulator and Transmit Filter......................................................................................... 7
4.8 Rx Data Retiming ................................................................................................................... 9
4.9 Tx Data Retiming.................................................................................................................. 10
5.
Application .............................................................................................................. 11
5.1 Line Interface........................................................................................................................ 11
6.
Performance Specification .................................................................................... 12
6.1 Electrical Performance ......................................................................................................... 12
6.2 Timing................................................................................................................................... 15
6.3 Packaging............................................................................................................................. 16
MXCOM, Inc. reserves the right to change specifications at any time and without notice
1998
MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
3
MX604 PRELIMINARY INFORMATION
1.
Block Diagram
XTAL/
CLOCK
XTAL
V
DD
V
BIAS
V
SS
RXAMPOUT
RXIN
Xtal Osc and
Clock Dividers
Energy
Detect
Mode
Control
Logic
Receive
Filter and
Equalizer
V
BIAS
FSK
De-modulator
Rx/Tx Data
Re-timing
Transmit Filter
and Output Buffer
FSK
Modulator
RXEQ
DET
M1
M0
RXD
CLK
RDY
TXD
TXOUT
Figure 1: Block Diagram
1998
MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
4
MX604 PRELIMINARY INFORMATION
2.
Signal List
Pin No.
Name
TN
1
2
5
6
7
8
11
12
13
XTAL
XTAL/CLOCK
M0
M1
RXIN
RXAMPOUT
TXOUT
V
SS
V
BIAS
output
input
input
input
input
output
output
power
output
Output of the on-chip Xtal oscillator inverter.
Input to the on-chip Xtal oscillator inverter.
A logic level input for setting the mode of the device.
See section 4.2
A logic level input for setting the mode of the device.
See section 4.2
Input to the Rx input amplifier.
Output of the Rx input amplifier.
Output of the FSK generator.
Negative supply (ground).
Internally generated bias voltage, held at V
DD
/2
when the device is not in 'Zero-Power' mode.
Should be decoupled to V
SS
by a capacitor
mounted close to the device pins.
A logic level input for enabling/disabling the
equalizer in the receive filter. See section 4.4
A logic level input for either the raw input to the FSK
Modulator or data to be re-timed depending on the
state of the M0, M1 and CLK inputs.
See section 4.9
A logic level input which may be used to clock data
bits in/out of the FSK Data Retiming block.
A logic level output carrying either the raw output of
the FSK Demodulator or re-timed characters
depending on the state of the M0, M1 and CLK
inputs. See section 4.8
A logic level output of the on-chip energy detect
circuit.
"Ready for data transfer" output of the on-chip data
retiming circuit. This open-drain active low output
may be used as an Interrupt Request/Wake-up
input to the associated
C.
An external pull-up
resistor should be connected between this output
and V
DD
.
The positive supply rail. Levels and thresholds
within the device are proportional to this voltage.
Should be decoupled to V
SS
by a capacitor
mounted close to the device pins.
No internal connections
Type
Description
P, DW
1
2
3
4
5
6
7
8
9
10
11
14
17
RXEQ
TXD
input
input
12
13
18
19
CLK
RXD
input
output
14
15
20
23
DET
RDY
output
output
16
24
V
DD
power
3, 4, 9, 10 ,15,
16, 21, 22
N/C
This device is capable of detecting and decoding small amplitude signals. Achieving the V
DD
and V
BIAS
decoupling and protection of the receive path from extraneous in-band signals is very important. It is
recommended that decoupling capacitors be placed so the connection between them and the device pins is
as short as possible. A ground plane protecting the receive path will help attenuate interfering signals.
1998
MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
v.23 Compatible Modem
5
MX604 PRELIMINARY INFORMATION
3.
External Components
V
DD
C1
X1
C2
XTAL
1
2
3
4
5
6
7
8
16
15
14
V
DD
RDY
DET
RXD
CLK
TXD
RXEQ
V
BIAS
R1
C3
XTAL/CLOCK
M0
From µC
M1
RXIN
RXAMPOUT
TXOUT
V
SS
MX604
13
12
11
10
9
C4
5%,
10%
10%
10%
R1
C1, C2
C3
C4
X1
Note 1
100k
18pF
0.1F
0.1F
3.579545MHz
Figure 2: Recommended External Components for Typical Application
External Components Notes:
1. A crystal frequency of 3.579545MHz
0.1%
is required for correct FSK operation. For best results, a
crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of V
DD
,
peak-peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator
design assistance, consult your crystal manufacturer. Operation of this device without a Xtal or Clock
input may cause device damage.
4.
4.1
General Description
Xtal Osc and Clock Dividers
Frequency and timing accuracy of the MX604 is determined by a 3.579545MHz clock present at the
XTAL/CLOCK pin. This may be generated by the on-chip oscillator inverter using the external components
C1, C2 and X1 of Figure 2, or it may be supplied from an external source to the XTAL/CLOCK input. If
supplied from an external source, C1, C2 and X1 should not be used.
The on-chip oscillator is disabled in the 'Zero-Power' mode.
If the clock is provided by an external source which is not always running, then the 'Zero-Power' mode must
be set when the clock is not available. Failure to observe this rule may cause a significant rise in the supply
current drawn by MX604 as well as generating undefined states of the RXD, DET and RDY outputs.
1998
MXCOM, INC.
Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480152.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
To/From µC
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
