19-0523; Rev 1; 2/11
KIT
ATION
EVALU
BLE
AVAILA
Octal, 12-Bit, 40Msps, 1.8V ADC
with Serial LVDS Outputs
General Description
Features
o
Excellent Dynamic Performance
69.9dB SNR at 5.3MHz
96dBc SFDR at 5.3MHz
95dB Channel Isolation
o
Ultra-Low Power
93mW per Channel (Normal Operation)
Fast 200μs Wake-Up Time from Standby
o
Serial LVDS Outputs
o
Pin-Selectable LVDS/SLVS (Scalable Low-Voltage
Signal) Mode
o
LVDS Outputs Support Up to 30 Inches FR-4
Backplane Connections
o
Test Mode for Digital Signal Integrity
o
Fully Differential Analog Inputs
o
Wide Differential Input Voltage Range (1.4V
P-P
)
o
On-Chip 1.24V Precision Bandgap Reference
o
Clock Duty-Cycle Equalizer
o
Compact, 100-Pin TQFP Package with Exposed
Pad
o
Evaluation Kit Available (Order MAX1436BEVKIT)
MAX1436B
The MAX1436B octal, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction incorporating a
fully differential signal path. This ADC is optimized for
low-power and high-dynamic performance in medical
imaging instrumentation and digital communications
applications. The MAX1436B operates from a 1.8V sin-
gle supply and consumes only 743mW (93mW per
channel) while delivering a 69.9dB (typ) signal-to-noise
ratio (SNR) at a 5.3MHz input frequency. In addition to
low operating power, the MAX1436B features a low-
power standby mode for idle periods.
An internal 1.24V precision bandgap reference sets the
full-scale range of the ADC. A flexible reference struc-
ture allows the use of an external reference for applica-
tions requiring increased accuracy or a different input
voltage range. The reference architecture is optimized
for low noise.
A single-ended clock controls the data-conversion
process. An internal duty-cycle equalizer compensates
for wide variations in clock duty cycle. An on-chip PLL
generates the high-speed serial low-voltage differential
signal (LVDS) clock.
The MAX1436B has self-aligned serial LVDS outputs for
data, clock, and frame-alignment signals. The output
data is presented in two’s complement or binary format.
The MAX1436B offers a maximum sample rate of
40Msps. See the
Pin-Compatible Versions
table below
for higher-speed versions. This device is available in a
small, 14mm x 14mm x 1mm, 100-pin TQFP package
with exposed pad and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Ordering Information
PART
MAX1436BECQ+D
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
100 TQFP-EP*
(14mm x 14mm x 1mm)
Applications
Ultrasound and Medical Imaging
Instrumentation
Multichannel Communications
+Denotes
a lead(Pb)-free/RoHS-compliant package.
D = Dry pack.
*EP
= Exposed pad.
Pin-Compatible Versions
PART
MAX1434
MAX1436
MAX1436B
MAX1437
MAX1438
SAMPLING
RATE (Msps)
50
40
40
50
65
RESOLUTION
(Bits)
10
12
12
12
12
POWER-
SAVE MODE
Power-down
Power-down
Standby
Power-down
Power-down
Pin Configuration appears at the end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Octal, 12-Bit, 40Msps, 1.8V ADC
with Serial LVDS Outputs
MAX1436B
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND)
AVDD.....................................................................-0.3V to +2.0V
CVDD.....................................................................-0.3V to +3.6V
OVDD ....................................................................-0.3V to +2.0V
IN_P, IN_N ..............................................-0.3V to (V
AVDD
+ 0.3V)
CLK ........................................................-0.3V to (V
CVDD
+ 0.3V)
OUT_P, OUT_N, FRAME_, CLKOUT_ ......-0.3V to (V
OVDD
+ 0.3V)
DT, SLVS/LVDS, LVDSTEST, PLL_,
T/B,
STBY,
REFIO, REFADJ, CMOUT...................-0.3V to (V
AVDD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
TQFP (derate 47.6mW/°C above +70°C) ................3809.5mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFP
Junction-to-Ambient Thermal Resistance (θ
JA
) ...........21°C/W
Junction-to-Case Thermal Resistance (θ
JC
) ..................2°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to
www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, external V
REFIO
= 1.24V, C
REFIO
= 0.1µF, C
REFP
= 10µF, C
REFN
= 10µF, f
CLK
= 40MHz (50% duty cycle), V
DT
= 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Notes 2, 3)
PARAMETER
DC ACCURACY (Note 4)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUTS (IN_P, IN_N)
Input Differential Range
Common-Mode Voltage Range
Common-Mode Voltage Range
Tolerance
Differential Input Impedance
Differential Input Capacitance
CONVERSION RATE
Maximum Conversion Rate
Minimum Conversion Rate
Data Latency
f
SMAX
f
SMIN
40
4.0
6.5
MHz
MHz
Cycles
R
IN
C
IN
V
ID
V
CMO
(Note 5)
Switched capacitor load
Differential input
1.4
0.76
±50
2
12.5
V
P-P
V
mV
kΩ
pF
N
INL
DNL
No missing codes over temperature
12
±0.4
±0.25
±3
±1
±0.5
±2.4
Bits
LSB
LSB
%FS
%FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
Octal, 12-Bit, 40Msps, 1.8V ADC
with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, external V
REFIO
= 1.24V, C
REFIO
= 0.1µF, C
REFP
= 10µF, C
REFN
= 10µF, f
CLK
= 40MHz (50% duty cycle), V
DT
= 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
f
1
= 5.3MHz at -6.5dBFS
f
2
= 6.3MHz at -6.5dBFS
f
1
= 5.3MHz at -6.5dBFS
f
2
= 6.3MHz at -6.5dBFS
Figure 11
Figure 11
Input at -20dBFS
Input at -0.5dBFS
IN_P = IN_N
t
OR
R
S
= 25Ω, C
S
= 50pF
79
66.5
66.5
MIN
TYP
69.9
69.6
69.9
69.6
11.3
11.3
96
90
-96
-92
89.8
96.6
< 0.4
1
100
100
0.44
1
-79
MAX
UNITS
MAX1436B
DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) (Note 4)
Signal-to-Noise Ratio
Signal-to-Noise and Distortion
(First 4 Harmonics)
Effective Number of Bits
Spurious-Free Dynamic Range
Total Harmonic Distortion
Intermodulation Distortion
Third-Order Intermodulation
Aperture Jitter
Aperture Delay
Small-Signal Bandwidth
Full-Power Bandwidth
Output Noise
Over-Range Recovery Time
INTERNAL REFERENCE
REFADJ Internal Reference-Mode
Enable Voltage
REFADJ Low-Leakage Current
REFIO Output Voltage
Reference Temperature
Coefficient
EXTERNAL REFERENCE
REFADJ External Reference-
Mode Enable Voltage
REFADJ High-Leakage Current
REFIO Input Voltage
REFIO Input Voltage Tolerance
REFIO Input Current
I
REFIO
(Note 6)
V
AVDD
-
0.1
200
1.24
±5
<1
V
µA
V
%
µA
V
REFIO
TC
REFIO
1.18
(Note 6)
1.5
1.24
120
1.30
0.1
V
mA
V
ppm/°C
SNR
SINAD
ENOB
SFDR
THD
IMD
IM3
t
AJ
t
AD
SSBW
LSBW
dB
dB
dB
dBc
dBc
dBc
dBc
ps
RMS
ns
MHz
MHz
LSB
RMS
Clock
cycle
_______________________________________________________________________________________
3
Octal, 12-Bit, 40Msps, 1.8V ADC
with Serial LVDS Outputs
MAX1436B
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, external V
REFIO
= 1.24V, C
REFIO
= 0.1µF, C
REFP
= 10µF, C
REFN
= 10µF, f
CLK
= 40MHz (50% duty cycle), V
DT
= 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Notes 2, 3)
PARAMETER
CMOUT Output Voltage
CLOCK INPUT (CLK)
Input High Voltage
Input Low Voltage
Clock Duty Cycle
Clock Duty-Cycle Tolerance
Input Leakage Current
Input Capacitance
DI
IN
DC
IN
0.8 x
V
AVDD
0.2 x
V
AVDD
Input at GND
Input at AVDD
5
R
TERM
= 100Ω
R
TERM
= 100Ω
R
TERM
= 100Ω, C
LOAD
= 5pF
R
TERM
= 100Ω, C
LOAD
= 5pF
R
TERM
= 100Ω
R
TERM
= 100Ω
R
TERM
= 100Ω, C
LOAD
= 5pF
R
TERM
= 100Ω, C
LOAD
= 5pF
250
1.125
350
350
205
220
320
320
200
60
450
1.375
5
80
Input at GND
Input at AVDD
5
V
CLKH
V
CLKL
50
±30
5
80
0.8 x
V
AVDD
0.2 x
V
AVDD
V
V
%
%
µA
pF
SYMBOL
V
CMOUT
CONDITIONS
MIN
TYP
0.76
MAX
UNITS
V
COMMON-MODE OUTPUT (CMOUT)
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS, STBY,
T/B)
Input Logic-High Voltage
Input Logic-Low Voltage
Input Leakage Current
Input Capacitance
Differential Output Voltage
Output Common-Mode Voltage
Rise Time (20% to 80%)
Fall Time (80% to 20%)
Differential Output Voltage
Output Common-Mode Voltage
Rise Time (20% to 80%)
Fall Time (80% to 20%)
STANDBY MODE (STBY)
STBY Fall to Output Enable
STBY Rise to Output Disable
t
ENABLE
t
DISABLE
µs
ns
V
IH
V
IL
DI
IN
DC
IN
V
OHDIFF
V
OCM
t
RL
t
FL
V
OHDIFF
V
OCM
t
RS
t
FS
V
V
µA
pF
mV
V
ps
ps
mV
mV
ps
ps
LVDS OUTPUTS (OUT_P, OUT_N), SLVS/LVDS = 0
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1
4
_______________________________________________________________________________________
Octal, 12-Bit, 40Msps, 1.8V ADC
with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, external V
REFIO
= 1.24V, C
REFIO
= 0.1µF, C
REFP
= 10µF, C
REFN
= 10µF, f
CLK
= 40MHz (50% duty cycle), V
DT
= 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Notes 2, 3)
PARAMETER
POWER REQUIREMENTS
AVDD Supply Voltage Range
OVDD Supply Voltage Range
CVDD Supply Voltage Range
V
AVDD
V
OVDD
V
CVDD
STBY = 0
AVDD Supply Current
I
AVDD
f
IN
= 19.3MHz STBY = 0, DT = 1
at -0.5dBFS
STBY = 1, standby,
no clock input
STBY = 0
OVDD Supply Current
I
OVDD
f
IN
= 19.3MHz STBY = 0, DT = 1
at -0.5dBFS
STBY = 1, standby,
no clock input
CVDD is used only to bias ESD-protection
diodes on CLK input, Figure 2
f
IN
= 19.3MHz at -0.5dBFS
(t
SAMPLE
/24)
- 0.15
1.7
1.7
1.7
1.8
1.8
1.8
337
337
37
76
99
16
0
743
864
(t
SAMPLE
/24)
+ 0.15
100
1.9
1.9
3.6
380
V
V
V
mA
mA
mA
µA
mA
mW
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1436B
CVDD Supply Current
Power Dissipation
I
CVDD
P
DISS
TIMING CHARACTERISTICS (Note 8)
Data Valid to CLKOUT Rise/Fall
CLKOUT Output-Width High
CLKOUT Output-Width Low
FRAME Rise to CLKOUT Rise
Sample CLK Rise to FRAME Rise
Crosstalk
Gain Matching
Phase Matching
C
GM
C
PM
t
OD
t
CH
t
CL
t
CF
t
SF
Figure 5 (Notes 7, 8)
Figure 5
Figure 5
Figure 4 (Note 8)
Figure 4 (Note 8)
(Note 4)
f
IN
= 5.3MHz (Note 4)
f
IN
= 5.3MHz (Note 4)
ns
ns
ns
ns
ns
dB
dB
Degrees
t
SAMPLE
/12
t
SAMPLE
/12
(t
SAMPLE
/24)
- 0.15
(t
SAMPLE
/2)
+ 1.1
-95
±0.1
±0.25
(t
SAMPLE
/24)
+ 0.15
(t
SAMPLE
/2)
+ 2.6
Note 2:
Specifications at T
A
≥
+25°C are guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design
and characterization and not subject to production testing.
Note 3:
All capacitances are between the indicated pin and GND, unless otherwise noted.
Note 4:
See definition in the
Parameter Definitions
section at the end of this data sheet.
Note 5:
See the
Common-Mode Output (CMOUT)
section.
Note 6:
Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the inter-
nal bandgap reference and enable external reference mode.
Note 7:
Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 8:
Guaranteed by design and characterization. Not subject to production testing.
_______________________________________________________________________________________
5
电机控制
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
