CAT25C32/64
32K/64K-Bit SPI Serial CMOS EEPROM
FEATURES
s
10 MHz SPI compatible
s
1.8 to 6.0 volt operation
s
Hardware and software protection
s
Low power CMOS technology
s
SPI modes (0,0 &1,1)
s
Commercial, industrial and automotive
s
1,000,000 program/erase cycles
s
100 year data tetention
s
Self-timed write cycle
s
8-pin DIP/SOIC and 14-pin TSSOP
s
64-Byte page write buffer
s
Block write protection
temperature ranges
– Protect 1/4, 1/2 or all of EEPROM array
DESCRIPTION
The CAT25C32/64 is a 32K/64K-Bit SPI Serial CMOS
EEPROM internally organized as 4Kx8/8Kx8 bits.
Catalyst’s advanced CMOS Technology substantially
reduces device power requirements. The CAT25C32/
64 features a 64-byte page write buffer. The device
operates via the SPI bus serial interface and is enabled
though a Chip Select (CS). In addition to the Chip Select,
the clock input (SCK), data in (SI) and data out (SO) are
PIN CONFIGURATION
DIP Package (P, L, GL)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
BLOCK DIAGRAM
i
D
SO
SI
CS
WP
HOLD
SCK
I/O
CONTROL
i
t
n
o
c
s
CS
SO
WP
VSS
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
CONTROL LOGIC
SOIC Package (S, V, GV)
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
d
e
u
n
Pin Name
SO
SCK
WP
V
CC
V
SS
CS
required to access the device. The
HOLD
pin may be
used to suspend any serial communication without
resetting the serial sequence. The CAT25C32/64 is
designed with software and hardware write protection
features including Block write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and
20-pin TSSOP packages.
a
P
CS
SO
NC
NC
NC
WP
V
SS
s
t
r
VCC
HOLD
NC
NC
NC
SCK
SI
TSSOP Package (U14, Y14)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
PIN FUNCTIONS
Function
Serial Data Output
Serial Clock
Write Protect
+1.8V to +6.0V Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
No Connect
SPI
CONTROL
LOGIC
XDEC
E
2
PROM
ARRAY
BLOCK
PROTECT
LOGIC
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
STATUS
REGISTER
SI
HOLD
NC
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1001, Rev. J
CAT25C32/64
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
SS1)
................... –2.0V to +V
CC
+2.0V
V
CC
with Respect to V
SS ................................
–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Min.
1,000,000
Max.
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB(5)
I
LI
i
D
I
LO
V
IL(3)
V
OL1
V
IH(3)
V
OH1
V
OL2
V
OH2
Doc. No. 1001, Rev. J
i
t
n
o
c
s
Parameter
Min.
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby)
Input Leakage Current
Output Leakage Current
Input Low Voltage
-1
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
d
e
u
n
2000
100
Limits
Typ.
Max.
10
2
1
2
3
V
CC
x 0.3
V
CC
+ 0.5
0.4
V
V
V
V
0.2
V
V
100
a
P
V
CC
= 5.0V
F
CLK
= 10MHz
Units
Cycles/Byte
Years
Volts
mA
s
t
r
Units
mA
mA
µA
µA
µA
Test Conditions
V
CC
= 5V @ 10MHz
SO=open; CS=Vss
CS
= V
CC
V
IN
= V
SS
or V
CC
V
OUT
= 0V to V
CC
,
CS = 0V
V
CC
x 0.7
V
CC
- 0.8
4.5V≤V
CC
<5.5V
I
OL
= 3.0mA
I
OH
= -1.6mA
1.8V≤V
CC
<2.7V
I
OL
= 150µA
I
OH
= -100µA
V
CC
-0.2
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Maximum standby current (I
SB
) = 10µA for the Automotive and Extended Automotive temperature range.
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C32/64
PIN CAPACITANCE
(1)
Applicable over recommended operating range from T
A
=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
C
OUT
C
IN
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI,
WP, HOLD)
Max.
8
6
Units
pF
pF
Conditions
V
OUT
=0V
V
IN
=0V
A.C. CHARACTERISTICS
Limits
Vcc=
1.8V-6.0V
SYMBOL PARAMETER
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(1)
t
FI(1)
t
HD
t
CD
t
WC
t
V
t
HO
t
DIS
t
HZ
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
HOLD
to Output Low Z
Input Rise Time
Input Fall Time
Min.
50
50
250
250
DC
Max.
V
CC
=
2.5V-6.0V
Min.
50
50
Max.
V
CC
=
4.5V-5.5V
Min.
20
20
Max.
HOLD
Setup Time
HOLD
Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
i
D
t
CS
t
CSS
t
CSH
Output Disable Time
HOLD
to Output High Z
CS
High Time
CS
Setup Time
CS
Hold Time
i
t
n
o
c
s
100
100
0
500
500
500
d
e
u
n
125
40
125
DC
40
1
3
DC
50
2
2
50
2
2
100
40
100
40
10
10
250
0
250
150
250
250
250
250
100
200
100
100
250
0
10
a
P
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
UNITS Conditions
s
t
r
Test
50
2
2
C
L
= 50pF
5
80
75
50
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1001, Rev. J
CAT25C32/64
FUNCTIONAL DESCRIPTION
The CAT25C32/64 supports the SPI bus data
transmission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25C32/64 to interface
directly with many of today’s popular microcontrollers.
The CAT25C32/64 contains an 8-bit instruction register.
(The instruction set and the operation codes are detailed
in the instruction set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
Figure 1. Sychronous Data Timing
V
IH
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C32/64. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C32/64. During a read cycle,
data is shifted out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
CS
V
IL
t
CSS
V
IH
SCK
V
IL
t
SU
V
IH
t
WH
t
H
SI
VIL
V
OH
SO
V
OL
Note: Dashed Line= mode (1, 1) — — — —
INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
i
D
i
t
n
o
c
s
HI-Z
VALID IN
d
e
u
n
t
WL
t
RI
tFI
t
V
t
HO
t
CSH
a
P
t
DIS
HI-Z
s
t
r
t
CS
Opcode
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Doc. No. 1001, Rev. J
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C32/64
the communication between the microcontroller and the
25C32/64. Opcodes, byte addresses, or data present on
the SI pin are latched on the rising edge of the SCK. Data
on the SO pin is updated on the falling edge of the SCK.
CS:
CS
Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25C32/
64 and
CS
high disables the CAT25C32/64.
CS
high
takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
write operation is underway). The CAT25C32/64 draws
ZERO current in the Standby mode. A high to low
transition on
CS
is required prior to any sequence being
initiated. A low to high transition on
CS
after a valid write
sequence is what initiates an internal write cycle.
WP:
WP
Write Protect
WP
is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When
WP
is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited.
WP
going low while
CS
is still low
STATUS REGISTER
7
WPEN
6
X
5
X
4
X
will interrupt a write to the status register. If the internal
write cycle has already been initiated,
WP
going low will
have no effect on any write operation to the status
register. The
WP
pin function is blocked when the WPEN
bit is set to 0.
HOLD:
HOLD
Hold
The
HOLD
pin is used to pause transmission to the
CAT25C32/64 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause,
HOLD
must be brought low while SCK
is low. The SO pin is in a high impedance state during the
time the part is paused, and transitions on the SI pins will
be ignored. To resume communication,
HOLD
is brought
high, while SCK is low.
(HOLD
should be held high any
time this function is not being used.)
HOLD
may be tied
high directly to V
cc
or tied to V
cc
through a resistor.
Figure 9 illustrates hold timing sequence.
BLOCK PROTECTION BITS
Status Register Bits
BP1
0
0
BP0
0
i
D
1
1
WPEN
0
0
1
1
X
X
WRITE PROTECT ENABLE OPERATION
i
t
n
o
c
s
1
0
1
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Array Address
Protected
None
d
e
u
n
3
2
BP1
BP0
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
5
a
P
1
WEL
Protection
No Protection
s
t
r
0
RDY
25C32: 0C00-0FFF
25C64:1800-1FFF
25C32: 800-0FFF
25C64:1000-1FFF
Quarter Array Protection
Half Array Protection
Full Array Protection
25C32: 0000-0FFF
25C64:0000-1FFF
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
Doc. No. 1001, Rev. J
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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