SU572644578E63R01
October 9, 2008
Ordering Information
Part Number
SG572644578E63R01
SM572644578E63R01
Description
64Mx72 (512MB), SDRAM, 168-pin DIMM, Registered, ECC, 64Mx4 Based, PC133, CL 3.0,
30.48mm, Green Module (RoHS Compliant).
64Mx72 (512MB), SDRAM, 168-pin DIMM, Registered, ECC, 64Mx4 Based, PC133, CL 3.0
30.48mm.
(All specifications of this device are subject to change without notice.)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SU572644578E63R01
October 9, 2008
Revision History
• October 9, 2008
Updated datasheet to the latest format.
Changed the datasheet part number from SM572648578E63R01 to SU572648578E63R01 because of the addition of a new
Module Process Technology.
Added SG572648578E63R01 to the Ordering Information on page 1.
Added SPD to pages 14~16.
• July 3, 2002
Modified Physical Dimensions on page 11.
• March 13, 2002
Modified Physical Dimensions on page 11.
• July 12, 2001
Modified AC Characteristics (t
RCD
) on page 7.
Modified Ordering Information (Cycle Time) on page 16.
• May 2, 2001
Datasheet released.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SU572644578E63R01
October 9, 2008
512MByte (64Mx72) Synchronous DRAM Module - 64Mx4 Based
168-pin DIMM, Registered, ECC
Features
•
•
•
•
•
•
•
•
Standard
Configuration
Cycle Time
CAS# Latency
Burst Length
Burst Type
Module Ranks
No. of Devices
:
:
:
:
:
:
:
:
PC133
ECC
7.5ns
3.0
1, 2, 4, 8, Full Page
Linear/Interleave
1 Rank of x4 devices
18
•
•
•
•
•
•
•
•
No. of Internal
Banks per SDRAM :
4
Operating Voltage :
3.3V
Refresh
:
8K/64ms
Device Physicals
:
400mil TSOP
Lead Finish
:
Gold
Length x Height
:
133.35mm x 30.48mm
No. of sides
:
Double-sided
Mating Connector (Examples)
Vertical
:
AMP - 5390074-1
SDRAM 168-pin DIMM Pin List
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Pin
Name
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
Pin
No.
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin
Name
CB1
V
SS
NC
NC
V
DD
WE#
DQMB0
DQMB1
CS0#
NC
V
SS
A0
A2
A4
A6
A8
A10/AP
BA1
V
DD
V
DD
CLK0
Pin
No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Pin
Name
V
SS
NC
CS2#
DQMB2
DQMB3
NC
V
DD
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
NC
Pin
No.
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin
Name
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CLK2
NC
WP
SDA
SCL
V
DD
Pin
No.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
Pin
Name
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
Pin
No.
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Pin
Name
CB5
V
SS
NC
NC
V
DD
CAS#
DQMB4
DQMB5
NC
RAS#
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
CLK1
A12
Pin
No.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
Pin
Name
V
SS
CKE0
NC
DQMB6
DQMB7
NC
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
NC
REGE
Pin
No.
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
Name
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CLK3
NC
SA0
SA1
SA2
V
DD
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SU572644578E63R01
October 9, 2008
Pin Description Table
Symbol
CLK0~CLK3
CKE0
CS0#, CS2#
RAS#, CAS#,
WE#
BA0, BA1
A0~A9, A10/AP,
A11~A12
Type
Input
Input
Input
Input
Input
Input
Polarity
Positive Edge
Active High
Active Low
Active Low
-
-
Function
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their associated clock.
Activates the SDRAM CLK signal when high and deactivates the CLK signal when low. By deactivating
the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables decoder when high. When
decoder is disabled, new commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the operations to be
executed by the SDRAM.
Selects which of the four internal SDRAM banks is activated.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at
the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA9, CA11) when
sampled at the rising clock edge. In addition to the column address, A10/AP is used to invoke autopre-
charge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1. If
AP is low, BA0 and BA1 are used to define which bank to precharge.
Data and Check Bit Input/Output pins.
Data strobe for input and output data.
The Register Enable pin is used to permit the DIMM to operate in Buffered mode (inputs re-driven asyn-
chronously) or Registered mode (signals re-driven to SDRAMs when clock rises, and held valid until next
rising clock).
These signals are tied on the system to either V
SS
or V
DD
to configure the serial SPD.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected
on the system board from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected on the sys-
tem board from the SCL bus line to V
DD
to act as a pullup.
Write protection.
Power and ground for the SDRAM input buffers and core logic.
No Connect.
DQ0~DQ63
CB0~CB7
DQMB0~
DQMB7
REGE
Input-
Output
Input
Input
-
Active High
Active High
(Reg. module
enable)
-
-
-
-
-
-
SA0~SA2
SDA
SCL
WP
V
DD,
V
SS
NC
Input
Input-
Output
Input
Input
Supply
-
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SU572644578E63R01
October 9, 2008
Block Diagram
RCS0#
RCKE0
RDQMB0
DQMB S# CKE
DQ0
DQ1
DQ2
DQ3
RDQMB0
DQMB S# CKE
DQ4
DQ5
DQ6
DQ7
RDQMB1
DQMB S# CKE
DQ8
DQ9
DQ10
DQ11
RDQMB1
DQMB S# CKE
DQ12
DQ13
DQ14
DQ15
RDQMB1
DQMB S# CKE
CB0
CB1
CB4
CB5
RDQMB4
DQMB S# CKE
DQ32
DQ33
DQ34
DQ35
RDQMB4
DQMB S# CKE
DQ36
DQ37
DQ38
DQ39
RDQMB5
DQMB S# CKE
DQ40
DQ41
DQ42
DQ43
RDQMB5
DQMB S# CKE
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
SD12
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
SD11
DQ56
DQ57
DQ58
DQ59
RDQMB7
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
SD17
I/O 0
I/O 1
I/O 2
I/O 3
SD10
DQ52
DQ53
DQ54
DQ55
RDQMB7
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
SD16
I/O 0
I/O 1
I/O 2
I/O 3
SD9
DQ48
DQ49
DQ50
DQ51
RDQMB6
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
SD15
I/O 0
I/O 1
I/O 2
I/O 3
SD4
CB2
CB3
CB6
CB7
RDQMB6
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
SD14
I/O 0
I/O 1
I/O 2
I/O 3
SD3
DQ28
DQ29
DQ30
DQ31
RDQMB5
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
SD13
I/O 0
I/O 1
I/O 2
I/O 3
SD2
DQ24
DQ25
DQ26
DQ27
RDQMB3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
SD8
I/O 0
I/O 1
I/O 2
I/O 3
SD1
DQ20
DQ21
DQ22
DQ23
RDQMB3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
SD7
I/O 0
I/O 1
I/O 2
I/O 3
SD0
DQ16
DQ17
DQ18
DQ19
RDQMB2
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
SD6
RDQMB2
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
SD5
RCS2#
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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