4M x 16-Bit Dynamic RAM
(8k, 4k & 2k Refresh, EDO-Version)
Advanced Information
•
•
•
•
HYB 3164165AT(L) -40/-50/-60
HYB 3165165AT(L) -40/-50/-60
HYB 3166165AT(L) -40/-50/-60
4 194 304 words by 16-bit organization
0 to 70 °C operating temperature
Hyper Page Mode - EDO - operation
Performance:
-40
t
RAC
t
CAC
t
AA
t
RC
t
HPC
RAS access time
CAS access time
Access time from address
Read/write cycle time
Hyper page mode (EDO)
cycle time
40
10
20
69
16
-50
50
13
25
84
20
-60
60
15
30
104
25
ns
ns
ns
ns
ns
•
•
Single + 3.3 V (± 0.3V) power supply
Low power dissipation:
-40
HYB3166165AT(L)
HYB3165165AT(L)
HYB3164165AT(L)
1008
756
612
-50
612
504
324
-60
450
360
324
mW
mW
mW
•
•
•
•
•
7.2 mW standby (TTL)
3.24 mW standby (MOS)
720
µA
standby for L-version
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and Self Refresh (L-version only
2 CAS / 1 WE byte control
8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165AT)
4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165AT)
2048 refresh cycles/ 32 ms , 11 R/ 11C addresses (HYB 3166165AT)
256ms refresh period for L-versions
Plastic Package:
P-TSOPII-50 400 mil
Semiconductor Group
1
6.97
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
This device is a 64 MBit dynamic RAM organized 4 194 304 x 16 bits. The device is fabricated on
an advanced first generation 64Mbit 0,35
µm
CMOS silicon gate process technology. The circuit
and process design allow this device to achieve high performance and low power dissipation. The
HYB3164(5)165AT operates with a single 3.3 +/-0.3V power supply and interfaces with either
LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB3164(5/6)165AT to be
packaged in 400mil wide TSOPII-50 package. These packages provide high system bit densities
and are compatible with commonly used automatic testing and insertion equipment. The
HYB3164(5/6)165ATL parts have a very low power „sleep mode“ supported by Self Refresh.
Ordering Information
Type
8k-refresh versions:
HYB 3164165AT-40
HYB 3164165AT-50
HYB 3164165AT-60
HYB 3164165ATL-50
HYB 3164165ATL-60
4k-refresh versions:
HYB 3165165AT-40
HYB 3165165AT-50
HYB 3165165AT-60
HYB 3165165ATL-50
HYB 3165165ATL-60
2k-refresh versions:
HYB 3166165AT-40
HYB 3166165AT-50
HYB 3166165AT-60
HYB 3166165ATL-50
HYB 3166165ATL-60
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
400 mil
400 mil
400 mil
400 mil
400 mil
EDO-DRAM (access time 40 ns)
EDO-DRAM (access time 50 ns)
EDO-DRAM (access time 60 ns)
EDO-DRAM (access time 50 ns)
EDO-DRAM (access time 60 ns)
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
400 mil
400 mil
400 mil
400 mil
400 mil
EDO-DRAM (access time 40 ns)
EDO-DRAM (access time 50 ns)
EDO-DRAM (access time 60 ns)
EDO-DRAM (access time 50 ns)
EDO-DRAM (access time 60 ns)
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
400 mil
400 mil
400 mil
400 mil
400 mil
EDO-DRAM (access time 40 ns)
EDO-DRAM (access time 50 ns)
EDO-DRAM (access time 60 ns)
EDO-DRAM (access time 50 ns)
EDO-DRAM (access time 60 ns)
Ordering
Code
Package
Descriptions
Semiconductor Group
2
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
Pin Configuration
P-TSOPII-50 (400 mil)
O
VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
N.C.
VCC
WE
RAS
N.C.
N.C.
N.C.
N.C.
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
.
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
I/O16
I/O15
I/O14
I/O13
VSS
I/O12
I/O11
I/O10
I/O9
N.C.
VSS
.
LCAS
UCAS
OE
N.C.
N.C.
A12/N.C. *
A11/N.C.**
A10
A9
A8
A7
A6
VSS
* Pin 33 is A12 for HYB 3164165AT(L) and N.C. for HYB 3165(6)165AT(L)
** Pin 32 is A11 for HYB 3164(5)165AT(L) and N.C. for HYB 3166165AT(L)
Pin Names
A0-A12
A0-A11
A0-A10
RAS
OE
I/O1-I/O16
UCAS, LCAS
WE
Vcc
Vss
Address Inputs for 8k-refresh version HYB 3164165T(L)
Address Inputs for 4k-refresh version HYB 3165165T(L)
Address Inputs for 2k-refresh version HYB 3166165T(L)
Row Address Strobe
Output Enable
Data Input/Output
Column Address Strobe
Read/Write Input
Power Supply ( + 3.3V)
Ground
Semiconductor Group
3
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
TRUTH TABLE
FUNCTION
Standby
Read:Word
Read:Lower Byte
Read:Upper Byte
Write:Word
(Early-Write)
Write:Lower Byte
(Early-Write)
Write:Upper Byte
(Early Write)
Read-Modify-
Write
Hyper Page Mode
1st
Read (Word)
Cycle
Hyper Page Mode 2nd
Read (Word)
Cycle
Hyper Page Mode
1st
Early Write(Word) Cycle
Hyper Page Mode 2nd
Early Write(Word) Cycle
Hyper Page Mode
1st
RMW
Cycle
Hyper Page Mode
2st
RMW
Cycle
RAS only refresh
CAS-before-RAS
refresh
Test Mode Entry
Hidden Refresh
(Read)
Hidden Refresh
(Write)
Self Refresh
(L-version only)
RAS LCAS UCAS WE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H-X
L
L
H
L
L
H
L
H-L
H-L
H-L
H-L
H-L
H-L
H
H-X
H
H
L
L
H
L
L
H-L
H-L
H-L
H-L
H-L
H-L
H
L
L
L
L
H
X
H
H
H
L
L
L
H-L
H
H
L
L
H-L
H-L
X
H
L
H
L
X
OE
X
L
L
L
X
X
X
ROW
ADD
X
ROW
ROW
ROW
ROW
ROW
ROW
COL
ADD
X
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
n/a
n/a
n/a
COL
COL
X
I/O1-
I/O16
High Impedance
Data Out
Lower Byte:Data Out
Upper-Byte:High-Z
Lower Byte:High-Z
Upper Byte:Data Out
Data In
Lower Byte:Data Out
Upper-Byte:High-Z
Lower Byte:High-Z
Upper Byte:Data Out
Data Out, Data In
Data Out
Data Out
Data In
Data In
Data Out, Data In
Data Out, Data In
High Impedance
High Impedance
High Impedance
Data Out
Data In
High Impedance
L - H ROW
L
L
X
X
ROW
n/a
ROW
n/a
L - H ROW
L - H n/a
X
X
X
L
X
X
ROW
X
X
ROW
ROW
X
H-L L
H-L L
L-H- L
L
L-H- L
L
H-L
L
Semiconductor Group
4
HYB3164(5/6)165AT(L)-40/-50/-60
4M x 16 EDO-DRAM
I/O1
I
/O2
I
/O16
WE
UCAS
LCAS
.
.
&
Data in
Buffer
No. 2 Clock
Generator
16
Data out
Buffer
16
OE
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Column
Address
Buffer(9)
9
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
16
Refresh
Counter (13)
13
Row
13
512
x16
Address
Buffers(13)
13
Decoder
8192
Row
Memory Array
8192x512x16
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3164165AT(L)
Semiconductor Group
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
