Micrel, Inc.
5V/3.3V PROGRAMMABLE
FREQUENCY SYNTHESIZER
(50MHz to 950MHz)
Precision Edge
®
SY89430V
Precision Edge
®
SY89430V
FEATURES
■
■
■
■
■
5V and 3.3V power supply options
50MHz to 950MHz differential PECL outputs
±25ps
peak-to-peak output jitter
Minimal frequency over-shoot
Synthesized architecture
Precision Edge
®
DESCRIPTION
The SY89430V is a general purpose, synthesized clock
source targeting applications that require both serial and
parallel interfaces. Its internal VCO will operate over a
range of frequencies from 400MHz to 950MHz. The
differential PECL output can be configured to be the VCO
frequency divided by 1, 2, 4 or 8. With the output configured
to divide the VCO frequency by 2, and with a 16MHz
external quartz crystal used to provide the reference
frequency, the output frequency can be specified in 1MHz
steps.
■
Serial 3 wire interface
■
Parallel interface for power-on
■
Internal quartz reference oscillator driven by quartz
crystal
■
Applications note (AN-07) for ease of design-ins
■
Available in 28-pin PLCC and SOIC packages
APPLICATIONS
■
■
■
■
■
■
■
■
Workstations
Advanced communications
High end consumer
High-performance computing
RISC CPU clock
Graphics pixel clock
Test equipment
Other high-performance processor-based
applications
Precision Edge is a registered trademark of Micrel, Inc.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
Rev.: H
Amendment: /0
1
Issue Date: January 2006
Micrel, Inc.
Precision Edge
®
SY89430V
PACKAGE/ORDERING INFORMATION
V
CC
(TTL)
GND (TTL)
V
CC_OUT
Ordering Information
(1)
Part Number
SY89430VJC
18
17
FOUT
GND
FOUT
TEST
Package
Type
J28-1
J28-1
Z28-1
Z28-1
J28-1
J28-1
Z28-1
Z28-1
Operating
Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Package
Marking
SY89430VJC
SY89430VJC
SY89430VZC
SY89430VZC
Lead
Finish
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
25 24 23 22 21 20 19
S
_CLOCK
S
_DATA
S
_LOAD
V
CC_QUIET
LOOP
_FILTER
LOOP_
REF
XTAL1
26
27
28
1
2
3
4
5
6
7
8
9
10 11
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
SY89430VJCTR
(2)
SY89430VZC
SY89430VZCTR
(2)
SY89430VJZ
(3)
SY89430VJZTR
(2, 3)
SY89430VZH
(3)
SY89430VZHTR
(2, 3)
PLCC
TOP VIEW
16
15
14
13
12
SY89430VJZ with
Matte-Sn
Pb-Free bar line indicator Pb-Free
SY89430VJZ with
Matte-Sn
Pb-Free bar line indicator Pb-Free
SY89430VZH with
Pb-Free bar line indicator
SY89430VZH with
Pb-Free bar line indicator
NiPdAu
Pb-Free
NiPdAu
Pb-Free
P
_LOAD
M[0]
M[1]
M[2]
28-Pin
PLCC (J28-1)
XTAL2
V
CC1
M[3]
M[0]
M[1]
M[2]
M[3]
M[4]
M[5]
M[6]
M[7]
M[8]
N[0]
N[1]
GND (TTL)
TEST
V
CC
(TTL)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
P
_LOAD
V
CC1
XTAL
2
XTAL
1
LOOP
_REF
LOOP
_FILTER
V
CC_QUIET
S
_LOAD
S
_DATA
S
_CLOCK
V
CC_OUT
FOUT
FOUT
GND
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
TOP VIEW
SOIC
Z28-1
22
21
20
19
18
17
16
15
28-Pin SOIC (Z28-1)
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge
®
SY89430V
BLOCK DIAGRAM
+3.3V
or
+5.0V
÷8
FREF
PLL
PHASE DETECTOR
VCO
10-25MHz
Fundamental
Crystal
PECL
OSC
÷M
400 – 950
MHz
÷N
FOUT
3 WIRE
INTERFACE
SERIAL
PARALLEL
INTERFACE
LOGIC
TEST
CONFIG INFO
DETAILED BLOCK DIAGRAM
150
3300pF
2
LOOP_FILTER
FREF
3
0.47µF
+3.3V
or
+5.0V
1
V
CC_QUIET
+3.3V
or
+5.0V
6, 21
V
CC1
LOOP_REF
÷8
PHASE DETECTOR
VCO
400 - 950
MHz
T110
÷N
(2,4,8,1)
V
CC_OUT
+3.3V
or
+5.0V
25
24
23
FOUT
FOUT
4
10–25MHz
Fundamental
Crystal
XTAL1
OSC
5
10pF
1
0
9-BIT ÷ M
COUNTER
L = LATCH
H = Transparent
XTAL2
FOUT ÷ 4 — 7
28
S_
LOAD
LATCH
LATCH
S_
CLOCK
÷ M — 6
LATCH
P_
LOAD
7
0
1
0
1
LOW — 5
FOUT — 4
÷M— 3
FREF — 2
20
TEST
S_
DATA
S_
CLOCK
27
26
9-BIT SR
2-BIT SR
3-BIT SR
HIGH — 1
0
8 -> 16
9
M[8:0]
17,18
2
N[1:0]
19,22
NOTE:
Pin numbers reference PLCC pinout.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge
®
SY89430V
PIN DESCRIPTIONS
INPUTS
XTAL1, XTAL2
These pins form an oscillator when connected to an external
crystal. The crystal is series resonant. See “AN-07” for
Crystal Interface Guideline.
S_
LOAD
This TTL pin loads the configuration latches with the contents
of the shift registers. The latches will be transparent when this
signal is HIGH; thus, the register data must be stable on the
HIGH-to-LOW transition of S_
LOAD
for proper operation.
S_
DATA
This TTL pin is the input to the serial configuration shift
registers.
S_
CLOCK
This TTL pin clocks the serial configuration shift registers. On
the rising edge of this signal, data from S_
DATA
is sampled.
/P_
LOAD
This TTL pin loads the configuration latches with the contents
of the parallel inputs. The latches will be transparent when this
signal is LOW; thus, the parallel data must be stable on the
LOW-to-HIGH transition of /P_
LOAD
for proper operation.
M[8:0]
These TTL pins are used to configure the PLL loop divider.
They are sampled on the LOW-to-HIGH transition of /P_
LOAD
.
M[8] is the MSB, M[0] is the LSB. The binary count on the M
pins equates to the divide-by value for the PLL.
N[1:0]
These TTL pins are used to configure the output divider
modulus. They are sampled on the LOW-to-HIGH transition
of /P_
LOAD
.
N[1:0]
00
01
10
11
Output Division
2
4
8
1
OUTPUTS
FOUT, FOUT
These differential positive-referenced ECL signals (PECL)
are the output of the synthesizer.
TEST
The function of this TTL output is determined by the serial
configuration bits T[2:0].
POWER
V
CC1
This is the positive supply for the chip and is normally
connected to +3.3V or +5.0V.
V
CC_OUT
This is the positive reference for the PECL outputs, FOUT and
/FOUT. It is constrained to be less than or equal to
VCC1
.
V
CC_QUIET
This is the positive supply for the PLL and should be as noise-
free as possible for low-jitter operation.
GND
These pins are the negative supply for the chip and are
normally all connected to ground.
OTHER
LOOP_FILTER
This is an analog I/O pin that provides the loop filter for the
PLL.
LOOP_REF
This is an analog I/O pin that provides a reference voltage for
the PLL.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge
®
SY89430V
WITH 16MHZ INPUT
VCO Frequency
(MHz)
400
402
404
406
•
•
•
944
946
948
950
256
M8
0
0
0
0
•
•
•
1
1
1
1
128
M7
1
1
1
1
•
•
•
1
1
1
1
64
M6
1
1
1
1
•
•
•
1
1
1
1
32
M5
0
0
0
0
•
•
•
0
0
0
0
16
M4
0
0
0
0
•
•
•
1
1
1
1
8
M3
1
1
1
1
•
•
•
1
1
1
1
4
M2
0
0
0
0
•
•
•
0
0
0
0
2
M1
0
0
1
1
•
•
•
0
0
1
1
1
M0
0
1
0
1
•
•
•
0
1
0
1
M Count
200
201
202
203
•
•
•
472
473
474
475
FUNCTIONAL DESCRIPTION
The internal oscillator uses the external quartz crystal as
the basis of its frequency reference. The output of the reference
oscillator is divided by eight before being sent to the phase
detector. With a 16MHz crystal, this provides a reference
frequency of 2MHz.
The VCO within the PLL operates over a range of 400–
950MHz. Its output is scaled by a divider that is configured by
either the serial or parallel interfaces. The output of this loop
divider is also applied to the phase detector.
The phase detector and loop filter force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M
(either too high or too low) the PLL will not achieve loop lock.
External loop filter components are utilized to allow for optimal
phase jitter performance.
The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. The
output divider is configured through either the serial or the
parallel interfaces and can provide one of four divider ratios
(1, 2, 4 or 8). This divider extends the performance of the part
while providing a 50% duty cycle.
The output driver is driven differentially from the output
divider and is capable of driving a pair of transmission lines
terminated in 50Ω to V
CC
–2volts. The positive reference for
the output driver is provided by a dedicated power pin
(V
CC_OUT
) to reduce noise induced jitter.
The configuration logic has two sections: serial and
parallel. The parallel interface uses the values at the M[8:0]
and N[1:0] inputs to configure the internal counters.
Normally, upon system reset, the P_
LOAD
input is held
LOW until some time after power becomes valid. With
S_
LOAD
held LOW, on the LOW-to-HIGH transition of
P_
LOAD
, the parallel inputs are captured. The parallel
interface has priority over the serial interface. Internal pull-
up resistors are provided on the M[8:0] and N[1:0] inputs to
reduce component count.
The serial interface logic is implemented with a 14-bit shift
register scheme. The register shifts once per rising edge of the
S_
CLOCK
input. The serial input S_
DATA
must meet set-up and
hold timing as specified in the AC parameters section of this
data sheet. With P_
LOAD
held HIGH, the configuration latches
will capture the value in the shift register on the HIGH-to-LOW
edge of the S_
LOAD
input. See the programming section for
more information.
The TEST output reflects various internal node values and
is controlled by the T[2:0] bits in the serial data stream. See
the programming subsection of this data sheet for more
information.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
5
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