Micrel, Inc.
5V/3.3V PROGRAMMABLE
FREQUENCY SYNTHESIZER
(25MHz to 400MHz)
Precision Edge
®
SY89429V
Precision Edge
®
SY89429V
FEATURES
■
■
■
■
■
■
3.3V and 5V power supply options
25MHz to 400MHz differential PECL outputs
50ps peak-to-peak output jitter
Minimal frequency over-shoot
Synthesized architecture
Serial 3-wire interface
Precision Edge
®
DESCRIPTION
The SY89429V is a general purpose, synthesized clock
source targeting applications that require both serial and
parallel interfaces. Its internal VCO will operate over a
range of frequencies from 400MHz to 800MHz. The
differential PECL output can be configured to be the VCO
frequency divided by 2, 4, 8 or 16. With the output configured
to divide the VCO frequency by 2, and with a 16MHz
external quartz crystal used to provide the reference
frequency, the output frequency can be specified in 1MHz
steps.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
■
Parallel interface for power-on
■
Internal quartz reference oscillator driven by quartz
crystal
■
Application Note (AN-07) for ease of design-ins
■
Available in 28-pin PLCC and SOIC packages
APPLICATIONS
■
■
■
■
■
■
■
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Workstations
Advanced communications
High end consumer
High-performance computing
RISC CPU clock
Graphics pixel clock
Test equipment
Other high-performance processor-based
applications
Precision Edge is a registered trademark of Micrel, Inc.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
Rev.: J
Amendment: /0
1
Issue Date: January 2006
Micrel, Inc.
Precision Edge
®
SY89429V
PACKAGE/ORDERING INFORMATION
GND (TTL)
GND
VCC (TTL)
VCC_OUT
Ordering Information
(1)
Part Number
SY89429VJC
18
17
FOUT
/FOUT
TEST
Package
Type
J28-1
J28-1
Z28-1
Z28-1
J28-1
J28-1
Z28-1
Z28-1
Operating
Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Package
Marking
SY89429VJC
SY89429VJC
SY89429VZC
SY89429VZC
Lead
Finish
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
25 24 23 22 21 20 19
S_CLOCK
S_DATA
S_LOAD
VCC_QUIET
LOOP_FILTER
LOOP_REF
XTAL1
26
27
28
1
2
3
4
5
6
7
8
9
10 11
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
SY89429VJCTR
(2)
SY89429VZC
SY89429VZCTR
(2)
SY89429VJZ
(3)
SY89429VJZTR
(2, 3)
SY89429VZH
(3)
SY89429VZHTR
(2, 3)
PLCC
TOP VIEW
16
15
14
13
12
SY89429VJZ with
Matte-Sn
Pb-Free bar line indicator Pb-Free
SY89429VJZ with
Matte-Sn
Pb-Free bar line indicator Pb-Free
SY89429VZH with
NiPdAu
Pb-Free bar line indicator Pb-Free
SY89429VZH with
NiPdAu
Pb-Free bar line indicator Pb-Free
VCC1
/P_LOAD
M[1]
M[2]
28-PinPLCC
(J28-1)
XTAL2
M[0]
M[3]
M[0]
M[1]
M[2]
M[3]
M[4]
M[5]
M[6]
M[7]
M[8]
N[0]
N[1]
GND (TTL)
TEST
VCC (TTL)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
SOIC
Z28-1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
/P_LOAD
VCC1
XTAL2
XTAL1
LOOP_REF
LOOP_FILTER
VCC_QUIET
S_LOAD
S_DATA
S_CLOCK
VCC_OUT
FOUT
/FOUT
GND
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
28-PinSOIC
(Z28-1)
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge
®
SY89429V
BLOCK DIAGRAM
+3.3V
or
+5.0V
FREF
÷
8
PHASE DETECTOR
PLL
VCO
10-25MHz
Fundamental
Crystal
PECL
÷
N
FOUT
OSC
÷
M
400 – 800MHz
3 WIRE
INTERFACE
SERIAL
PARALLEL
INTERFACE
LOGIC
TEST
CONFIG INFO
DETAILED BLOCK DIAGRAM
150
Ω
2
LOOP_FILTER
FREF
3300pF
3
0.47
µ
F
+3.3V
or
+5.0V
1
V
CC_QUIET
+3.3V
or
+5.0V
6, 21
V
CC1
LOOP_REF
÷
8
PHASE DETECTOR
VCO
400 - 800
MHz
T110
÷
N
+3.3V
or
+5.0V
V
CC_OUT
25
24
23
FOUT
/FOUT
4
10Ð25MHz
Fundamental
Crystal
XTAL1
OSC
XTAL2
L = LATCH
H = Transparent
1
0
5
10pF
9-BIT
÷
M
COUNTER
(2,4,8,16)
S_
LOAD
/P_
LOAD
28
7
LATCH
FOUT Ö 4 Ñ 7
LATCH
S_
CLOCK
Ö M Ñ 6
LATCH
0
1
0
1
LOW Ñ 5
FOUT Ñ 4
ÖMÑ 3
FREF Ñ 2
HIGH Ñ 1
20
TEST
S_
DATA
S_
CLOCK
27
26
9-BIT SR
2-BIT SR
3-BIT SR
0
8 -> 16
9
M[8:0]
17,18
2
N[1:0]
19,22
NOTE:
Pin numbers reference PLCC pinout.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge
®
SY89429V
PIN DESCRIPTIONS
INPUTS
XTAL1, XTAL2
These pins form an oscillator when connected to an external
crystal. The crystal is series resonant. See “AN-07” for Crystal
Interface Guideline.
S
_LOAD
This TTL pin loads the configuration latches with the contents
of the shift registers. The latches will be transparent when this
signal is HIGH; thus, the register data must be stable on the
HIGH-to-LOW transition of S
_LOAD
for proper operation.
S
_DATA
This TTL pin is the input to the serial configuration shift
registers.
S
_CLOCK
This TTL pin clocks the serial configuration shift registers. On
the rising edge of this signal, data from S
_DATA
is sampled.
/P
_LOAD
This TTL pin loads the configuration latches with the contents
of the parallel inputs. The latches will be transparent when this
signal is LOW: Thus, the parallel data must be stable on the
LOW-to-HIGH transition of /P
_LOAD
for proper operation.
During power up, hold /P
_LOAD
low with a valid M count on
M[0] - M[8] until supplies have stabilized.
M[8:0]
These TTL pins are used to configure the PLL loop divider.
They are sampled on the LOW-to-HIGH transition of /P
_LOAD
.
M[8] is the MSB, M[0] is the LSB. The binary count on the M
pins equates to the divide-by value for the PLL.
N[1:0]
These TTL pins are used to configure the output divider
modulus. They are sampled on the LOW-to-HIGH transition
of /P
_LOAD
.
N[1:0]
00
01
10
11
Output Division
2
4
8
16
OUTPUTS
FOUT, /FOUT
These differential positive-referenced ECL signals (PECL)
are the output of the synthesizer.
TEST
The function of this TTL output is determined by the serial
configuration bits T[2:0].
POWER
V
CC1
This is the positive supply for the chip and is normally
connected to +3.3V or +5.0V.
V
CC_OUT
This is the positive reference for the PECL outputs, FOUT and
/FOUT. It is constrained to be less than or equal to V
CC1
.
V
CC_QUIET
This is the positive supply for the PLL and should be as noise-
free as possible for low-jitter operation.
GND
These pins are the negative supply for the chip and are
normally all connected to ground.
OTHER
LOOP_FILTER
This is an analog I/O pin that provides the loop filter for the
PLL.
LOOP_REF
This is an analog I/O pin that provides a reference voltage for
the PLL.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge
®
SY89429V
WITH 16MHZ INPUT
VCO Frequency
(MHz)
400
402
404
406
•
•
•
794
796
798
800
M Count
200
201
202
203
•
•
•
397
398
399
400
256
M8
0
0
0
0
•
•
•
1
1
1
1
128
M7
1
1
1
1
•
•
•
1
1
1
1
64
M6
1
1
1
1
•
•
•
0
0
0
0
32
M5
0
0
0
0
•
•
•
0
0
0
0
16
M4
0
0
0
0
•
•
•
0
0
0
1
8
M3
1
1
1
1
•
•
•
1
1
1
0
4
M2
0
0
0
0
•
•
•
1
1
1
0
2
M1
0
0
1
1
•
•
•
0
1
1
0
1
M0
0
1
0
1
•
•
•
1
0
1
0
FUNCTIONAL DESCRIPTION
The internal oscillator uses the external quartz crystal as the
basis of its frequency reference. The output of the reference
oscillator is divided by eight before being sent to the phase
detector. With a 16MHz crystal, this provides a reference frequency
of 2MHz.
The VCO, within the PLL, operates over a range of 400–
800MHz. Its output is scaled by a divider that is configured by
either the serial or parallel interfaces. The output of this loop
divider is also applied to the phase detector.
The phase detector and loop filter force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low) the PLL will not achieve loop lock. External loop
filter components are utilized to allow for optimal phase jitter
performance.
The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. The output
divider is configured through either the serial or the parallel
interfaces and can provide one of four divider ratios (2, 4, 8 or 16).
This divider extends the performance of the part while providing
a 50% duty cycle.
The output driver is driven differentially from the output divider
and is capable of driving a pair of transmission lines terminated
in 50Ω to V
CC
–2 volts. The positive reference for the output driver
is provided by a dedicated power pin (V
CC_OUT
) to reduce noise
induced jitter.
The configuration logic has two sections: serial and parallel.
The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. Normally, upon
system reset, the /P
_LOAD
input is held LOW until some time
after power becomes valid. With S
_LOAD
held LOW, on the
LOW-to-HIGH transition of /P
_LOAD
, the parallel inputs are
captured. The parallel interface has priority over the serial
interface. Internal pull-up resistors are provided on the M[8:0]
and N[1:0] inputs to reduce component count.
The serial interface logic is implemented with a 14-bit shift
register scheme. The register shifts once per rising edge of the
S
_CLOCK
input. The serial input S
_DATA
must meet set-up and
hold timing as specified in the AC parameters section of this data-
sheet. With /P
_LOAD
held HIGH, the configuration latches will
capture the value in the shift register on the HIGH-to-LOW edge
of the S
_LOAD
input. See the programming section for more
information.
The TEST output reflects various internal node values and is
controlled by the T[2:0] bits in the serial data stream. See the
programming subsection of this data sheet for more information.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
5
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