Micrel, Inc.
3.3V/5V 3.2Gbps CML
LOW-POWER LIMITING
POST AMPLIFIER w/TTL SD
DESCRIPTION
SY88983V
SY88983V
FEATURES
s
Multi-Rate up to 3.2Gbps operation
s
Wide gain-bandwidth product
• 38dB differential gain
• 2.2GHz 3dB bandwidth
s
Low noise 50
Ω
CML data outputs
• 800mV
pp
output swing
• 60ps edge rates
• 5ps
rms
typ. random jitter
• 15ps
pp
typ. deterministic jitter
s
Chatter-free Signal Detect (SD) output
• 4.6dB electrical hysteresis
• OC-TTL output with internal 5k
Ω
pull-up resistor
s
Programmable SD sensitivity using single external
resistor
s
Internal 50
Ω
data input termination
s
TTL EN input allows feedback from SD
s
Wide operating range
• Single 3.3V
±
10% or 5V
±
10% power supply
• –40
°
C to +85
°
C industrial temperature range
s
Available in tiny 10-pin MSOP (3mm) and 16-pin MLF™
(3mm
×
3mm) packages
s
NOT RECOMMENDED for New Designs!
APPLICATIONS
s
1.25Gbps and 2.5Gbps Gigabit Ethernet
s
1.062Gbps and 2.125Gbps Fibre Channel
s
155Mbps, 622Mbps, 1.25Gbps and 2.5Gbps
SONET/SDH
s
Gigabit interface converter (GBIC)
s
Small form factor (SFF) and small form factor pluggable
(SFP) transceivers
s
Parallel 10G Ethernet
s
High-gain line driver and line receiver
The SY88983V low-power limiting post amplifier is
designed for use in fiber optic receivers. The device connects
to typical transimpedance amplifiers (TIAs). The linear signal
output from TIAs can contain significant amounts of noise
and may vary in amplitude over time. The SY88983V
quantizes these signals and outputs typically 800mV
pp
voltage-limited waveforms.
The SY88983V operates from a single +3.3V
±10%
or
+5V
±10%
power supply, over the industrial temperature of
–40°C to +85°C. With its wide bandwidth and high gain,
signals with data rates up to 3.2Gbps and as small as
10mV
pp
can be amplified to drive devices with CML inputs
or AC-coupled PECL inputs.
The SY88983V generates a signal detect (SD) open-
collector TTL output with internal 5kΩ pull-up resistor. A
programmable signal detect level set pin (SD
LVL
) sets the
sensitivity of the input amplitude detection. SD asserts high
if the input amplitude rises above the threshold set by SD
LVL
and de-asserts low otherwise. SD can be fed back to the
enable (EN) input to maintain output stability under a loss-
of-signal condition. EN de-asserts the true output signal
without removing the input signal. Typically, 4.6dB SD
hysteresis is provided to prevent chattering.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
FUNCTIONAL BLOCK DIAGRAM
D
IN
50Ω
/D
IN
Limiting
Amplifer
CML
Buffer
D
OUT
/D
OUT
TYPICAL PERFORMANCE
3.3V, 25°C, 10mV
PP
Input
@2.5Gbps 2
23
–1 PRBS, R
LOAD
= 50Ω to V
CC
V
REF
V
CC
GND
2.8kΩ
V
CC
—1.3V
Level
Detect
TTL
Buffer
EN
V
CC
Output Swing
(75mV/div.)
5kΩ
OC-TTL
Buffer
SD
SD
LVL
TIME (100ps/div.)
MLF and
MicroLeadFrame
are trademarks of Amkor Technology, Inc.
February 2005
1
M9999-020205
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY88983V
PACKAGE/ORDERING INFORMATION
VCC
EN
SDLVL
VCC
Ordering Information
Part Number
Package
Type
K10-1
K10-1
MLF-16
MLF-16
Operating
Range
Industrial
Industrial
Industrial
Industrial
Package
Marking
983V
983V
983V
983V
16 15 14 13
DIN
GND
GND
/DIN
1
2
3
4
5 6 7 8
VCC
VREF
SD
VCC
12
11
10
9
DOUT
GND
GND
/DOUT
SY88983VKI
SY88983VKITR
(1)
SY88983VMI
SY88983VMITR
(1)
Note:
1. Tape and Reel.
16-Pin MLF™ (MLF-16)
EN 1
DIN 2
/DIN 3
VREF 4
SDLVL 5
10 VCC
9 DOUT
8 /DOUT
7 SD
6 GND
10-Pin MSOP (K10-1)
PIN DESCRIPTION
Pin Number
(MSOP)
1
2, 3
4
5
Pin Number
(MLF™)
15
1, 4
6
14
Pin Name
EN
DIN, /DIN
VREF
SDLVL
Input:
Default is
maximum sensitivity.
Ground
Open-Collector:
TTL Output with
internal 5kΩ pull-up
resistor.
Differential CML Output
Power Supply
Type
TTL Input:
Default is high.
Differential Data Input
Pin Function
Enable: De-asserts true data output when low.
Differential data input. Each pin internally terminates to
V
REF
through 50Ω.
Reference Voltage: Bypass with 0.01µF low ESR
capacitor from V
REF
to V
CC
to stabilize SD
LVL
and V
REF
.
Signal Detect Level Set: A resistor from this pin to V
CC
sets the threshold for the data input amplitude at which
the SD output will be asserted.
Device ground. Exposed pad must be connected to same
potential as ground pins for MLF-16.
Signal Detect: Asserts high when the data input
amplitude rises above the threshold set by SD
LVL
.
6
7
2, 3, 10, 11,
Exposed Pad
7
GND
SD
8, 9
10
9, 12
5, 8, 13, 16
DOUT, /DOUT
VCC
Differential data output.
Positive power supply. Bypass with 0.1µF0.01µF low
ESR capacitors. 0.01µF capacitors should be as close to
V
CC
pins as possible.
February 2005
2
M9999-020205
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY88983V
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) ....................................... 0V to +7.0V
EN, SD
LVL
Voltage .................................................0 to V
CC
D
IN
, /D
IN
Current ......................................................
±10mA
D
OUT
, /D
OUT
Current ................................................
±25mA
SD Current .................................................................
±5mA
V
REF
Current ..............................................................
±1mA
Storage Temperature (T
S
) ....................... –65°C to +150°C
Lead Temperature (soldering, 10 sec.) ..................... 220°C
Operating Ratings
(2)
Supply Voltage (V
CC
) .............................. +3.0V to +3.6V or
............................................................ +4.5V to +5.5V
Ambient Temperature (T
A
) ......................... –40°C to +85°C
Junction Temperature (T
J
) ....................... –40°C to +120°C
Package Thermal Resistance
(3)
MLF™
(θ
JA
) Still-Air .................................................... 61°C/W
(ψ
JB
) ................................................................ 38°C/W
MSOP
(θ
JA
) Still-Air .................................................. 113°C/W
(ψ
JB
) ................................................................ 74°C/W
DC ELECTRICAL CHARACTERISTICS
V
CC
= 3.0V to 3.6V or 4.5V to 5.5V; R
LOAD
= 50Ω to V
CC
; T
A
= –40°C to +85°C; typical values at V
CC
= 3.3V, T
A
= 25°C.
Symbol
I
CC
I
CC
V
REF
SD
LVL
V
OH
V
OL
V
OFFSET
Z
O
Z
I
Parameter
Power Supply Current
(4)
Power Supply Current
(5)
V
REF
Voltage
SD
LVL
Level
Output HIGH Voltage
Output LOW Voltage
Differential Output Offset
Single-Ended Output Impedance
Single-Ended Input Impedance
40
40
50
50
Note 6
Note 6
V
REF
V
CC
–0.020 V
CC
–0.005
Condition
3.3V
5V
3.3V
5V
Min
Typ
19
21
32
38
V
CC
–1.3
V
CC
V
CC
±80
60
60
V
CC
–0.400 V
CC
–0.275
Max
28
31
53
58
Units
mA
mA
mA
mA
V
V
V
V
mV
Ω
Ω
TTL DC ELECTRICAL CHARACTERISTICS
V
CC
= 3.0V to 3.6V or 4.5V to 5.5V; R
LOAD
= 50Ω to V
CC
; T
A
= –40°C to +85°C; typical values at V
CC
= 3.3V, T
A
= 25°C.
Symbol
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Notes:
1. Permanent device damage may occur if
“Absolute Maximum Ratings”
are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to
“Absolute Maximum Ratings”
conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Thermal performance assumes use of 4-layer PCB. If applicable, exposed pad must be soldered (or equivalent) to the device’s most negative
potential on the PCB.
4. Excludes current of CML output stage. See
“Detailed Description.”
5. Total device current with no output load.
6. Output levels are based on a 50Ω to V
CC
load impedance. If the load impedance is different, the output level will be changed.
February 2005
Parameter
SD Output HIGH Level
SD Output LOW Level
EN Input HIGH Voltage
EN Input LOW Voltage
EN Input HIGH Current
EN Input LOW Current
Condition
Sourcing 100µA
Sinking 2mA
Min
2.4
Typ
Max
V
CC
0.5
Units
V
V
V
2.0
0.8
V
IN
= 2.7V
V
IN
= V
CC
V
IN
= 0.5V
–0.3
20
100
V
µA
µA
mA
3
M9999-020205
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY88983V
AC ELECTRICAL CHARACTERISTICS
V
CC
= 3.0V to 3.6V or 4.5V to 5.5V; R
LOAD
= 50Ω to V
CC
; T
A
= –40°C to +85°C; typical values at V
CC
= 3.3V, T
A
= 25°C.
Symbol
HYS
PSRR
t
OFF
t
ON
t
r
, t
f
t
JITTER
V
ID
V
OD
V
SR
A
V(Diff)
B
–3dB
S
21
Notes:
7. Electrical signal.
8. With input signal V
ID
> 50mV
p-p
and 50Ω load.
9. Deterministic jitter measured using K28.5 pattern at 2.488Gbps, V
ID
= 10mV
p-p
. Random jitter measured using K28.7 pattern at 2.488Gbps, V
ID
=
10mV
p-p
.
10. Input is a 200MHz square wave, t
r
< 300ps, 50Ω load. V
ID
≥
14mV
p-p
.
11. This is the detectable range of input amplitudes that can de-assert SD. The input amplitude to assert SD is 2–8dB higher than the de-assert
amplitude. See
“Typical Operating Characteristics”
for a graph showing how to choose a particular R
SDLVL
for a particular SD de-assert, and its
associated assert, amplitude.
Parameter
SD Hysteresis
Power Supply Rejection Ratio
SD Release Time
SD Assert Time
Differential Output Rise/Fall Time
(20% to 80%)
Deterministic
Random
Differential Input Voltage Swing
Differential Output Voltage Swing
SD Sensitivity Range
Differential Voltage Gain
3dB Bandwidth
Single-Ended Small Signal-Gain
Condition
Note 7
Min
2
Typ
4.6
35
0.1
0.2
60
Max
8
Units
dB
dB
µs
µs
ps
ps
p-p
ps
rms
0.5
0.5
120
Note 8
Note 9
10
Note 10
Note 11
550
10
32
38
2.2
26
32
800
50
15
5
1800
mV
p-p
mV
p-p
mV
p-p
dB
GHz
dB
TYPICAL OPERATING CHARACTERISTICS
V
CC
= 3.3V, GND = 0V, T
A
= 25°C unless otherwise stated.
90
80
70
V
ID
(mV
P-P
)
60
50
40
30
20
10
SD Assert/Deassert Level
vs. R
SDLVL
ASSERT
DEASSERT
0
10
100
1000 10000 100000
R
SDLVL
February 2005
4
M9999-020205
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY88983V
DETAILED DESCRIPTION
The SY88983V low power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from –40°C to +85°C. Signals with data rates up to 3.2Gbps
and as small as 10mV
p-p
can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88983V generates
an SD output, allowing feedback to EN for output stability.
SD
LVL
sets the sensitivity of the input amplitude detection.
Input Amplifier/Buffer
The SY88983V’s inputs are internally terminated with 50Ω
to V
REF
. Unless they are not affected by this internal
termination scheme, upstream devices need to be
AC-coupled to the SY88983V’s inputs. Figure 2 shows a
simplified schematic of the input stage.
The high sensitivity of the input amplifier allows signals
as small as 10mV
p-p
to be detected and amplified. The
input amplifier allows input signals as large as 1800mV
p-p
.
Input signals are linearly amplified with a typically 38dB
differential voltage gain. Since it is a limiting amplifier, the
SY88983V outputs typically 800mV
p-p
voltage-limited
waveforms for input signals that are greater than 10mV
p-p
.
Applications requiring the SY88983V to operate with high-
gain should have the upstream TIA placed as close as
possible to the SY88983V’s input pins to ensure the best
performance of the device.
Output Buffer
The SY88983V’s CML output buffer is designed to drive
50Ω lines. The output buffer requires appropriate termination
for proper operation. An external 50Ω resistor to V
CC
or
equivalent for each output pin provides this. Figure 3 shows
a simplified schematic of the output stage and includes an
appropriate termination method. Of course, driving a
downstream device with a CML input that is internally
terminated with 50Ω to V
CC
eliminates the need for external
termination. As noted in the previous section, the amplifier
outputs typically 800mV
p-p
waveforms across 25Ω total
loads. The output buffer, thus, switches typically 16mA tail-
current. Figure 4 shows the power supply current
measurement, which excludes the 16mA tail-current.
Signal Detect
The SY88983V generates a chatter-free signal detect
(SD) open-collector TTL output with internal 5kΩ pull-up
resistor as shown in Figure 5. SD is used to determine that
the input amplitude is large enough to be considered a
valid input. SD asserts high if the input amplitude rises
above the threshold set by SD
LVL
and de-asserts low
otherwise. SD can be fed back to the enable (EN) input to
maintain output stability under a loss-of-signal condition.
EN de-asserts low the true output signal without removing
the input signals. Typically, 4.6dB SD hysteresis is provided
to prevent chattering.
Signal Detect-Level Set
A programmable signal detect-level set pin (SD
LVL
) sets
the threshold of the input amplitude detection. Connecting
an external resistor between V
CC
and SD
LVL
sets the voltage
at SD
LVL
. This voltage ranges from V
CC
to V
REF
. The
external resistor creates a voltage divider between V
CC
and
V
REF
as shown in Figure 6. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The smaller the external resistor, implying a smaller voltage
difference from SD
LVL
to V
CC
, lowers the SD sensitivity.
Hence, larger input amplitude is required to assert SD.
“Typical Operating Characteristics”
shows the relationship
between the input amplitude detection sensitivity and the
SD
LVL
setting resistor.
Hysteresis
The SY88983V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V
2IN
/R for an
electrical signal. Hence, the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
hence, the ratios also change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the data sheet. The SY88983V provides typically 2.3dB
SD optical hysteresis. As the SY88983V is an electrical
device, this data sheet refers to hysteresis in electrical terms.
With 4.6dB SD hysteresis, a voltage factor of 1.7 is required
to assert SD from its de-assert value.
February 2005
5
M9999-020205
hbwhelp@micrel.com or (408) 955-1690
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