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A54SX72A-CQ256I: 产品描述Field Programmable Gate Array, 6036 CLBs, 108000 Gates, CMOS, CQFP256, CERAMIC, QFP-256; 产品类别可编程逻辑器件可编程逻辑; 文件大小2MB，共83页; 制造商Microsemi; 官网地址https://www.microsemi.com

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A54SX72A-CQ256I概述

Field Programmable Gate Array, 6036 CLBs, 108000 Gates, CMOS, CQFP256, CERAMIC, QFP-256

A54SX72A-CQ256I规格参数

参数名称	属性值
厂商名称	Microsemi
包装说明	QFF,
Reach Compliance Code	compliant
其他特性	72000 TYPICAL GATES AVAILABLE
CLB-Max的组合延迟	1.3 ns
JESD-30 代码	S-CQFP-F256
长度	36 mm
可配置逻辑块数量	6036
等效关口数量	108000
端子数量	256
最高工作温度	85 °C
最低工作温度	-40 °C
组织	6036 CLBS, 108000 GATES
封装主体材料	CERAMIC, METAL-SEALED COFIRED
封装代码	QFF
封装形状	SQUARE
封装形式	FLATPACK
可编程逻辑类型	FIELD PROGRAMMABLE GATE ARRAY
认证状态	Not Qualified
座面最大高度	2.69 mm
最大供电电压	2.75 V
最小供电电压	2.25 V
标称供电电压	2.5 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	FLAT
端子节距	0.5 mm
端子位置	QUAD
宽度	36 mm

A54SX72A-CQ256I文档预览

v4.0



SX-A Family FPGAs

Le a di n g- E d ge P er f o r m a n ce

u e

• 250 MHz System Performance

• 350 MHz Internal Performance

• 3.8 ns Clock-to-Out (Pad-to-Pad)

S p e ci f i c a t i on s

•

12,000 to 108,000 Available System Gates

Up to 360 User-Programmable I/O Pins

Up to 2,012 Dedicated Flip-Flops

0.22

/0.25

CMOS Process Technology

• Configurable I/O Support for 3.3V/5V PCI, 5V TTL,

3.3V LVTTL, 2.5V LVCMOS2

• 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input

Tolerance and 5V Drive Strength

• Devices Support Multiple Temperature Grades

• Configurable Weak-Resistor Pull-up or Pull-down for

Outputs at Power-up

• Individual Output Slew Rate Control

• Up to 100% Resource Utilization and 100% Pin Locking

• Deterministic, User-Controllable Timing

• Unique In-System Diagnostic and Verification Capability

with Silicon Explorer II

• Boundary Scan Testing in Compliance with IEEE

Standard 1149.1 (JTAG)

• Actel’s Secure Programming Technology with FuseLock™

Prevents Reverse Engineering and Design Theft

Fe a t ur es

• Hot-Swap Compliant I/Os

• Power-up/down Friendly (No Sequencing Required for

Supply Voltages)

• 66 MHz PCI Compliant

• Single-Chip Solution

• Nonvolatile

SX - A P r od u ct P r o f i l e

Device

A54SX08A

A54SX16A

A54SX32A

A54SX72A

Capacity

Typical Gates

8,000

16,000

32,000

72,000

System Gates

12,000

24,000

48,000

108,000

Logic Modules

768

1,452

2,880

6,036

Combinatorial Cells

512

924

1,800

4,024

Dedicated Flip-Flops

256

528

1,080

2,012

Maximum Flip-Flops

512

990

1,980

4,024

Maximum User I/Os

130

180

249

360

Global Clocks

Quadrant Clocks

Boundary Scan Testing

Yes

3.3V/5V PCI

Yes

Clock-to-Out

4.2 ns

4.6 ns

4.7 ns

5.8 ns

Input Set-Up (External)

0 ns

Speed Grades

–F, Std, –1, –2, –3 –F, Std, –1, –2, –3 –F, Std, –1, –2, –3 –F, Std, –1, –2, –3

Temperature Grades

C, I, A

C, I, M, A

Package

(by pin count)

208

PQFP

208

100, 144

100, 144, 176

—

TQFP

100, 144

—

329

—

PBGA

—

256, 484

144, 256

144, 256, 484

FBGA

144

208, 256

CQFP*

Note:

For more information about the CQFP package options, refer to the

HiRel SX-A

datasheet at:

www.actel.com/documents/HRSXADS.pdf

A p r i l 20 0 3

S X -A F a m il y F P GA s

O r d e r i n g I nf o r m a t i o n

A54SX16

208

Application (Temperature Range)

Blank = Commercial (0 to +70°C)

= Industrial (–40 to +85°C)

M = Military (–55 to +125°C)

A = Automotive (–40 to +125°C)

Package Lead Count

Package Type

BG = 1.27mm Plastic Ball Grid Array

FG = 1.0mm Fine Pitch Ball Grid Array

PQ = Plastic Quad Flat Pack

TQ = Thin (1.4mm) Quad Flat Pack

CQ = Ceramic Quad Flat Pack*

Speed Grade

Blank = Standard Speed

–1 = Approximately 15% Faster than Standard

–2 = Approximately 25% Faster than Standard

–3 = Approximately 35% Faster than Standard

–F = Approximately 40% Slower than Standard

A = 0.22µ/0.25µ CMOS Technology

Part Number

A54SX08A

A54SX16A

A54SX32A

A54SX72A

12,000 System Gates

24,000 System Gates

48,000 System Gates

108,000 System Gates

*For more information about the CQFP package options, refer to the

HiRel SX-A

datasheet at:

www.actel.com/documents/HRSXADS.pdf

Pl a s t i c D e vi c e Re so u r ce s

User I/Os (including clock buffers)

Device

A54SX08A

A54SX16A

A54SX32A

A54SX72A

PQFP

208-Pin

130

175

174

171

TQFP

100-Pin

—

TQFP

144-Pin

113

—

TQFP

176-Pin

—

147

—

PBGA

329-Pin

—

249

—

FBGA

144-Pin

111

—

FBGA

256-Pin

—

180

203

FBGA

484-Pin

—

249

360

Contact your Actel sales representative for product availability.

Package Definitions

PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, PBGA = 1.27mm Plastic Ball Grid Array, FBGA = 1.0mm Fine Pitch Ball

Grid Array

v4.0

SX - A F a m ily F P GA s

Pr od uc t P l a n

Speed Grade**

–F

A54SX08A Device

100-Pin Thin Quad Flat Pack (TQFP)

144-Pin Thin Quad Flat Pack (TQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

144-Pin Fine Pitch Ball Grid Array (FBGA)

A54SX16A Device

100-Pin Thin Quad Flat Pack (TQFP)

144-Pin Thin Quad Flat Pack (TQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

144-Pin Fine Pitch Ball Grid Array (FBGA)

256-Pin Fine Pitch Ball Grid Array (FBGA)

A54SX32A Device

100-Pin Thin Quad Flat Pack (TQFP)

144-Pin Thin Quad Flat Pack (TQFP)

176-Pin Thin Quad Flat Pack (TQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

208-Pin Ceramic Quad Flat Pack (CQFP)*

256-Pin Ceramic Quad Flat Pack (CQFP)*

144-Pin Fine Pitch Ball Grid Array (FBGA)

256-Pin Fine Pitch Ball Grid Array (FBGA)

329-Pin Plastic Ball Grid Array (PBGA)

484-Pin Fine Pitch Ball Grid Array (FBGA)

A54SX72A Device

208-Pin Plastic Quad Flat Pack (PQFP)

208-Pin Ceramic Quad Flat Pack (CQFP)*

256-Pin Ceramic Quad Flat Pack (CQFP)*

256-Pin Fine Pitch Ball Grid Array (FBGA)

✔

–

✔

–

✔

–

✔

–

✔

Std

–1

–2

–3

Application

†

•

484-Pin Fine Pitch Ball Grid Array (FBGA)

✔

Contact your Actel sales representative for product availability.

*For more information about the CQFP package options, refer to the

HiRel SX-A

datasheet at:

www.actel.com/documents/HRSXADS.pdf

Applications: C = Commercial

Availability:

✔

= Available

**Speed Grade: –1 = Approx. 15% faster than Standard

I = Industrial

–2 = Approx. 25% faster than Standard

M = Military

–3 = Approx. 35% faster than Standard

A = Automotive

–F = Approx. 40%

slower

than Standard

† Only Std, –1, –2 Speed Grade

•

Only Std, –1 Speed Grade

v4.0

S X -A F a m il y F P GA s

G en er al D e sc r i p t i on

Actel’s SX-A family of FPGAs features a sea-of-modules

architecture that delivers high device performance. SX-A

devices simplify design time, enable dramatic reductions in

design costs and power consumption, and further decrease

time-to-market for performance-intensive applications.

Actel’s SX-A architecture features two types of logic

modules, the combinatorial cell (C-cell) and the register

cell (R-cell), each optimized for fast and efficient mapping

of synthesized logic functions. The routing and interconnect

resources are in the metal layers above the logic modules,

providing optimal use of silicon. This enables the entire

floor of the device to be spanned with an uninterrupted grid

of fine-grained, synthesis-friendly logic modules (or

“sea-of-modules”), which reduces the distance signals have

to travel between logic modules. To minimize signal

propagation delay, SX-A devices employ both local and

general routing resources. The high-speed local routing

resources (DirectConnect and FastConnect) enable very

fast local signal propagation that is optimal for fast

counters, state machines, and datapath logic. The general

system of segmented routing tracks allows any logic module

in the array to be connected to any other logic or I/O

module. Within this system, propagation delay is minimized

by limiting the number of antifuse interconnect elements to

five (90 percent of connections typically use only three or

fewer antifuses). The unique local and general routing

structure featured in SX-A devices gives fast and predictable

performance, allows 100% pin-locking with full logic

utilization, enables concurrent PCB development, reduces

design time, and allows designers to achieve performance

goals with minimum effort.

Further complementing SX-A’s flexible routing structure is a

hardwired, constantly loaded clock network that has been

tuned to provide fast clock propagation with minimal clock

skew. Additionally, the high performance of the internal

logic has eliminated the need to embed latches or flip-flops

in the I/O cells to achieve fast clock-to-out or fast input

set-up times. SX-A devices have easy-to-use I/O cells that do

not require HDL instantiation, facilitating design re-use and

reducing design and verification time.

S X - A F a m i l y A r c hi t ec t u r e

The SX-A family architecture was designed to satisfy

performance

and

integration

requirements

for

production-volume designs in a broad range of applications.

P r ogr am m abl e I nte rc onnec t E lem en t

The SX-A family provides efficient use of silicon by locating

the routing interconnect resources between the top two

metal layers (Figure

1).

This completely eliminates the

channels of routing and interconnect resources between

logic modules (as implemented on SRAM FPGAs and

previous generations of antifuse FPGAs), and enables the

entire floor of the device to be spanned with an

uninterrupted grid of logic modules.

Routing Tracks

Amorphous Silicon/

Dielectric Antifuse

Metal 4

Tungsten Plug Via

Metal 3

Tungsten Plug Via

Metal 2

Metal 1

Tungsten Plug Contact

Silicon Substrate

Note:

A54SX72A has four layers of metal with the antifuse between Metal 3 and Metal 4. A54SX08A, A54SX16A, and

A54SX32A have three layers of metal with antifuse between Metal 2 and Metal 3.

Figure 1 •

SX-A Family Interconnect Elements

v4.0

SX - A F a m ily F P GA s

Interconnection between these logic modules is achieved

using Actel’s patented metal-to-metal programmable

antifuse interconnect elements. The antifuses are normally

open circuit and, when programmed, form a permanent

low-impedance connection.

The extremely small size of these interconnect elements

gives the SX-A family abundant routing resources and

provides excellent protection against design pirating.

Reverse engineering is virtually impossible because it is

extremely difficult to distinguish between programmed and

unprogrammed antifuses, and since SX-A is a nonvolatile,

single-chip solution, there is no configuration bitstream to

intercept.

Additionally, the interconnect (i.e., the antifuses and metal

tracks) have lower capacitance and lower resistance than

any other device of similar capacity, leading to the fastest

signal propagation in the industry.

Logi c Modul e Des ign

modules, the register cell (R-cell) and the combinatorial

cell (C-cell).

The R-cell contains a flip-flop featuring asynchronous clear,

asynchronous preset, and clock enable (using the S0 and S1

lines) control signals (Figure

2).

The R-cell registers

feature programmable clock polarity selectable on a

while allowing mapping of synthesized functions into the

SX-A FPGA. The clock source for the R-cell can be chosen

from either the hardwired clock, the routed clocks, or

internal logic.

The C-cell implements a range of combinatorial functions of

up to five inputs (Figure

3 on page 6).

Inclusion of the DB

input and its associated inverter function increases the

number of combinatorial functions that can be implemented

in a single module from 800 options (as in previous

architectures) to more than 4,000 in the SX-A architecture.

An example of the improved flexibility enabled by the

inversion capability is the ability to integrate a 3-input

exclusive-OR function into a single C-cell. This facilitates

construction of 9-bit parity-tree functions with 1.9 ns

propagation delays. At the same time, the C-cell structure is

extremely synthesis friendly, simplifying the overall design

and reducing synthesis time.

The SX-A family architecture is described as a

“sea-of-modules” architecture because the entire floor of

the device is covered with a grid of logic modules with

virtually no chip area lost to interconnect elements or

routing. Actel’s SX-A family provides two types of logic

Routed

Data Input S1

PRE

DirectConnect

Input

HCLK

CLKA,

CLKB,

Internal Logic

CKS

CKP

CLR

Figure 2 •

R-Cell

v4.0

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A54SX72A-CQ256I相似产品对比

	A54SX72A-CQ256I	A54SX72A-1CQ256I	A54SX72A-2CQ256I	A54SX72A-FCQ256I
描述	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, CMOS, CQFP256, CERAMIC, QFP-256	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, CMOS, CQFP256, CERAMIC, QFP-256	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, CMOS, CQFP256, CERAMIC, QFP-256	Field Programmable Gate Array, 6036 CLBs, 108000 Gates, CMOS, CQFP256, CERAMIC, QFP-256
厂商名称	Microsemi	Microsemi	Microsemi	Microsemi
包装说明	QFF,	QFF,	QFF,	QFF,
Reach Compliance Code	compliant	compliant	compliant	compliant
其他特性	72000 TYPICAL GATES AVAILABLE	72000 TYPICAL GATES AVAILABLE	72000 TYPICAL GATES AVAILABLE	72000 TYPICAL GATES AVAILABLE
CLB-Max的组合延迟	1.3 ns	1.1 ns	1 ns	1.8 ns
JESD-30 代码	S-CQFP-F256	S-CQFP-F256	S-CQFP-F256	S-CQFP-F256
长度	36 mm	36 mm	36 mm	36 mm
可配置逻辑块数量	6036	6036	6036	6036
等效关口数量	108000	108000	108000	108000
端子数量	256	256	256	256
最高工作温度	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C
组织	6036 CLBS, 108000 GATES	6036 CLBS, 108000 GATES	6036 CLBS, 108000 GATES	6036 CLBS, 108000 GATES
封装主体材料	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
封装代码	QFF	QFF	QFF	QFF
封装形状	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	FLATPACK	FLATPACK	FLATPACK	FLATPACK
可编程逻辑类型	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	2.69 mm	2.69 mm	2.69 mm	2.69 mm
最大供电电压	2.75 V	2.75 V	2.75 V	2.75 V
最小供电电压	2.25 V	2.25 V	2.25 V	2.25 V
标称供电电压	2.5 V	2.5 V	2.5 V	2.5 V
表面贴装	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子形式	FLAT	FLAT	FLAT	FLAT
端子节距	0.5 mm	0.5 mm	0.5 mm	0.5 mm
端子位置	QUAD	QUAD	QUAD	QUAD
宽度	36 mm	36 mm	36 mm	36 mm

A54SX72A-CQ256I

A54SX72A-CQ256I概述

A54SX72A-CQ256I规格参数

A54SX72A-CQ256I文档预览

A54SX72A-CQ256I相似产品对比

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