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AN-9719
Applying Fairchild Power Switch (FPS™) FSL1x7 to
Low- Power Supplies
1. Introduction
The highly integrated FSL-series consists of an integrated
current-mode Pulse Width Modulator (PWM) and an
avalanche-rugged 700V SenseFET. It is specifically
designed for high-performance offline Switched Mode
Power Supplies (SMPS) with minimal external components.
The features of the integrated PWM controller include a
proprietary green-mode function providing off-time
modulation to linearly decrease the switching frequency at
light-load conditions to minimize standby power
consumption. The PWM controller is manufactured using
the BiCMOS process to further reduce power consumption.
The green mode and burst mode functions with a low
operating current (2mA in green mode) maximize light-load
efficiency so that the power supply can meet stringent
standby power regulations.
The FSL-series has a built-in synchronized slope
compensation to achieve stable peak-current-mode control.
The proprietary external line compensation ensures constant
output power limit over a wide AC input voltage range,
90V
AC
to 264V
AC
, and helps optimize the power stage.
Many protection functions; such as open–loop / overload
protection (OLP), over-voltage protection (OVP), and over-
temperature protection (OTP); are fully integrated into FSL-
series. These features improve the SMPS reliability without
increasing system cost.
Compared to a discrete MOSFET and controller or RCC
switching converter solution, the FSL-series reduces total
component count, converter size, and weight while
increasing efficiency, productivity, and system reliability.
These devices provide a basic platform for design of cost-
effective flyback converters.
Figure 1. Typical Application Circuit
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
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AN-9719
APPLICATION NOTE
2. Device Block Description
2.1 Startup Circuit
For startup, the HV pin is connected to the line input or bulk
capacitor through external resistor R
HV
, as shown in Figure
2. Typical startup current is 3.5mA and it charges the V
DD
capacitor (C
DD
) through resistor R
HV
. The startup current
turns off when the V
DD
capacitor voltage reaches V
DD-ON
.
The V
DD
capacitor maintains V
DD
until the auxiliary
winding of the transformer provides the operating current.
2.3 Green Mode Operation
The FSL-series uses feedback voltage (V
FB
) as an indicator
of the output load and modulates the PWM frequency, as
shown in Figure 4, such that the switching frequency
decreases as load decreases. In heavy-load conditions, the
switching frequency is 100kHz. Once V
FB
decreases below
V
FB-N
(2.5V), the PWM frequency starts to linearly decrease
from 100kHz to 18kHz to reduce the switching losses. As
V
FB
decreases below V
FB-G
(2.4V), the switching frequency
is fixed at 18kHz and FSL-series enters “deep” green mode
to reduce the standby power consumption. As V
FB
decreases
below V
FB-ZDC
(2.1V), FSL-series enters into burst-mode
operation. When V
FB
drops below V
FB-ZDC
, FSL-series stops
switching and the output voltage starts to drop, which
causes the feedback voltage to rise. Once V
FB
rises above
V
FB-ZDC
, switching resumes. Burst mode alternately enables
and disables switching, thereby reducing switching loss to
improve power saving, as shown in Figure 5.
Figure 2. Startup Circuit
2.2 Soft-Start
The FSL-series has internal soft-start circuit that slowly
increases the SenseFET current during startup. The typical
soft-start time is 5ms, during which the V
Limit
level is
increased in six steps to smoothly establish the required
output voltage, as shown in Figure 3. It also helps prevent
transformer saturation and reduce stress on the secondary
diode during startup.
Figure 4. PWM Frequency
Figure 3. Soft-Start Function
Figure 5. Bust-Mode Operation
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
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2
AN-9719
APPLICATION NOTE
2.4 Constant Power Control
To constantly limit the output power of the converter, high /
low line compensation is included. Sensing the converter
input voltage through the VIN pin, the high / low line
compensation function generates a line-voltage-dependent
peak-current-limit threshold voltage for constant power
control, as shown in Figure 6.
2.5.3 Overload Protection (OLP)
When the upper branch of the voltage divider for the shunt
regulator (KA431 shown) is open circuit, as shown in
Figure 7, or an output over-current or short occurs; there is
no current flowing through the opto-coupler transistor. V
FB
(feedback voltage) pulls up to 6V. When the feedback
voltage is above 4.6V for longer than 56ms, OLP is
triggered. This protection is also triggered when the SMPS
output drops below the nominal value longer than 56ms due
to the overload condition.
Figure 6. Constant Power Control
2.5 Protection Functions
The FSL-series provides full protection functions to prevent
the power supply and the load from being damaged. The
protection features is shown in Table 1.
Table 1.
Protection Functions
FSL127H
OVP
OTP
OLP
VIN-H
VIN-L
Latch
Latch
Auto Restart
Latch
Auto Restart
FSL137H
Latch
Latch
Auto Restart
Latch
Auto Restart
Figure 7. OLP Operator
2.5.1 V
DD
Over-Voltage Protection (OVP)
V
DD
over-voltage protection prevents IC damage caused by
over voltage on the V
DD
pin. The OVP is triggered when
V
DD
reaches 28V. It has debounce time (typically 130µs) to
prevent false trigger by switching noise.
2.5.2 Over-Temperature Protection (OTP)
The SenseFET and the control IC integration make
temperature detection of the SenseFET easier. When the
junction temperature exceeds approximately 142°C, thermal
shutdown is activated.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
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3
AN-9719
APPLICATION NOTE
3. Design Example
Flyback converters have two kinds of operation modes;
Continuous Conduction Mode (CCM) and Discontinuous
Conduction Mode (DCM). Each has its own advantages and
disadvantages. In general, DCM generates lower stress for
the rectifier diodes, since the diodes are operating at zero
current just before becoming reverse biased and the reverse
recovery loss is minimized. The transformer size can be
reduced using DCM because the average energy storage is
low compared to CCM. However, DCM causes high RMS
current, which severely increases the conduction loss of the
MOSFET for low line condition. For standby auxiliary
power supply applications with low output voltage and
minimal reverse recovery of Schottky diode, it is typical to
design the converter such that the converter operates in
CCM to maximize efficiency.
This section presents a design procedure using the Figure 1
schematic as a reference. An offline SMPS with 12W
nominal output power has been selected as the example.
[STEP-1] Define the System Specifications
[STEP-2] Determine Input Capacitor (C
IN
) and Input
Voltage Range
It is typical to select the input capacitor as 2~3μF per watt
of peak input power for the universal input range (85-
265V
RMS
) and 1μF per watt of peak input power for the
European input range (195V-265V
RMS
). With the input
capacitor chosen, the minimum input capacitor voltage at
nominal-load condition is obtained as:
2·
· 1
·
(2)
where D
CH
is the input capacitor charging duty ratio defined
in Figure 8, which is typically about 0.2.
The maximum input capacitor voltage is given as:
√2
(3)
When designing a power supply,
specifications should be determined first:
Line Voltage Range (V
Line Frequency (f
L
)
Nominal Output Power (P
O
)
and
V
the
)
following
Figure 8. Input Capacitor Voltage Waveform
(Design Example)
By choosing 20μF for input
Estimate Efficiencies for Nominal Load (
η
).
The power conversion efficiency must be estimated to
calculate the input power for nominal load condition. If
no reference data is available, set
η
= 0.7~0.75 for low-
voltage output applications and
η
= 0.8~0.85 for high-
voltage output applications.
With the estimated efficiency, the input power for peak
load condition is given by:
capacitor, the minimum input voltage for nominal load
is obtained as:
2·
· 1
·
15 · 1
20 · 10
0.2
· 60
2 · 90
79
η
(Design Example)
The specifications of the target
(1)
The maximum input voltage is obtained as:
√2 ·
√2 · 264
373
system are:
90V
V
264V
V
Line frequency (f ) = 60Hz
Nominal output power (P ) = 12W (12V/1A)
Estimated efficiency (η) = 0.8
[STEP-3] Determine the Reflected Output Voltage (V
RO
)
η
12
0.8
15
When the MOSFET is turned off, the input voltage (V
IN
),
together with the output voltage reflected to the primary
(V
RO
), are imposed across the MOSFET, as shown in Figure
9. With a given V
RO
, the maximum duty cycle (D
MAX
) and
the nominal MOSFET voltage (V
DSNOM
) are obtained as:
(4)
(5)
·
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
(6)
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AN-9719
APPLICATION NOTE
(Design Example)
As can be seen in Table 2, it is
recommended to use rectifier diode with 100V voltage
rating to maximize efficiency. Assuming that the
nominal voltages of MOSFET and diode are less than
80% of their voltage rating, the reflected output voltage
is given as:
·
373 · 12
0.85
12
0.8 · 100
80
373 · 12 0.85
68
70.5
0.8 · 700
560
560
By determining
Figure 9. Output Voltage Reflected to the Primary
373
187
as 74V,
74
74
79
0.48
74
447
As can be seen in Equation 5, the voltage stress across
MOSFET can be reduced by reducing V
RO
. However, this
increases the voltage stresses on the rectifier diodes in the
secondary side, as shown in Equation 6. Therefore, V
RO
should be determined by a balance between the voltage
stresses of MOSFET and diode. Especially for low output
voltage applications, the rectifier diode forward-voltage
drop is a dominant factor determining the power supply
efficiency. Therefore, the reflected output voltage should be
determined such that rectifier diode forward voltage can be
minimized. Table 2 shows the forward-voltage drop for
Schottky diodes with different voltage rating.
The actual drain voltage and diode voltage rise above the
nominal voltage is due to the leakage inductance of the
transformer as shown in Figure 9. It is typical to set V
RO
such that V
DSNOM
and V
DONOM
are 70~80% of voltage
ratings of MOSFET and diode, respectively.
373
·
373 · 12 0.85
74
[STEP-4] Determine
Inductance (L
M
)
the
12
76.8
Primary-Side
Transformer
The transformer primary-side inductance is determined for
the minimum input voltage and nominal-load condition.
With the D
MAX
from Step-3, the primary-side inductance
(L
M
) of the transformer is obtained as:
·
2·
·
·
(7)
Table 2.
Diode Forward-Voltage Drop for Different
Voltage Ratings (3A Schottky Diode)
Part Name
SB320
SB330
SB340
SB350
SB360
SB380
SB3100
VRRM
20V
30V
40V
50V
60V
80V
100V
VF
0.5V
where f
SW
is the switching frequency and K
RF
is the ripple
factor at minimum input voltage and nominal load
condition, defined as shown in Figure 10.
For DCM operation, K
RF
= 1, and, for CCM operation, K
RF
< 1. The ripple factor is closely related to the transformer
size and the RMS value of the MOSFET current. Even
though the conduction loss in the MOSFET can be reduced
by reducing the ripple factor, too small a ripple factor forces
an increase in transformer size. When designing the flyback
converter to operate in CCM, it is reasonable to set K
RF
=
0.25-0.5 for the universal input range and K
RF
= 0.4-0.8 for
the European input range.
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0.74V
0.85V
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
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