K4S280432I
K4S280832I
K4S281632I
Synchronous DRAM
128Mb I-die SDRAM Specification
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.1 May 2006
K4S280432I
K4S280832I
K4S281632I
Synchronous DRAM
Year
2005
2006
- Final spec release.
- Added 5ns speed bin for x16
History
Revision History
Revision
1.0
1.1
Month
October
May
2 of 14
Rev. 1.1 May 2006
K4S280432I
K4S280832I
K4S281632I
Synchronous DRAM
8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
• RoHS compliant for Pb-free Package
•
•
•
•
GENERAL DESCRIPTION
The K4S280432I / K4S280832I / K4S281632I is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x
8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No.
K4S280432I-T(U)C/L75
K4S280832I-T(U)C/L75
K4S281632I-T(U)C/L50
K4S281632I-T(U)C/L60
K4S281632I-T(U)C/L75
Orgainization
32Mb x 4
16Mb x 8
8Mb x 16
8Mb x 16
8Mb x 16
Max Freq.
133MHz (CL=3)
133MHz (CL=3)
200MHz (CL=3)
166MHz (CL=3)
133MHz (CL=3)
LVTTL
54pin TSOP(II)
Interface
Package
Organization
32Mx4
16Mx8
8Mx16
Row Address
A0~A11
A0~A11
A0~A11
Column Address
A0-A9, A11
A0-A9
A0-A8
Row & Column address configuration
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Rev. 1.1 May 2006
K4S280432I
K4S280832I
K4S281632I
Package Physical Dimension
Synchronous DRAM
0~8°C
0.25
TYP
0.010
#54
#28
0.45~0.75
0.018~0.030
0.05
MIN
0.002
11.76±
0.20
0.463±
0.008
22.62
MAX
0.891
22.22
0.875
0.10
MAX
0.004
(
±
0.10
±
0.004
0.125
+0.075
-0.035
+0.003
0.005
-0.001
0.21
0.008
±
0.05
±
0.002
1.00
0.039
±
0.10
±
0.004
1.20
MAX
0.047
0.71
)
0.028
0.30
-0.05
0.012
+0.004
-0.002
+0.10
0.80
0.0315
54Pin TSOP(II) Package Dimension
4 of 14
Rev. 1.1 May 2006
( 0.50 )
0.020
#1
#27
10.16
0.400
K4S280432I
K4S280832I
K4S281632I
FUNCTIONAL BLOCK DIAGRAM
Synchronous DRAM
I/O Control
LWE
LDQM
Data Input Register
Bank Select
8M x 4 / 4M x 8 / 2M x 16
Sense AMP
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
Programming Register
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Timing Register
LWCBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
5 of 14
Rev. 1.1 May 2006
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