MX29LV400C T/B
MX29LV800C T/B
MX29LV160C T/B
SINGLE VOLTAGE 3V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• Byte/Word mode switchable:
- 524,288 x8 / 262,144 x16 (MX29LV400C)
- 1,048,576 x8 / 524,288 x16 (MX29LV800C)
- 2,097,152 x8 / 1,048,576 x16 (MX29LV160C)
• Sector Structure
- 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x 1
64K-Byte x 7 (MX29LV400C), 64K-Byte x 15 (MX29LV800C), 64K-Byte x 31 (MX29LV160C)
- Provides sector protect function to prevent program or erase operation in the protected sector
- Provides chip unprotect function to allow code changing
- Provides temporary sector unprotect function for code changing in previously protected sector
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 250mA from -1V to Vcc + 1V
• Low Vcc write inhibit : Vcc <= 1.4V
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
•
Fully compatible with MX29LV400B/MX29LV800B/MX29LV160B device
PERFORMANCE
• High Performance
- Fast access time: 45R (MX29LV400C and MX29LV800C only), 55R/70/90ns
- Fast program time: 7us/word typical utilizing accelerate function
- Fast erase time: 0.7s/sector, 15s/chip (typical, MX29LV160C)
• Low Power Consumption
- Low active read current: 10mA (typical) at 5MHz
- Low standby current: 200nA (typical)
• Minimum 100,000 erase/program cycle
• 10 years data retention
SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being erased
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
PACKAGE
• 44-Pin SOP
• 48-Pin TSOP
• 48-Ball CSP
•
All Pb-free devices are RoHS Compliant
P/N:PM1300
REV. 1.1, AUG. 17, 2006
1
MX29LV400C T/B
MX29LV800C T/B
MX29LV160C T/B
PIN DESCRIPTION
SYMBOL
A0~A17
Q0~Q14
Q15/A-1
CE#
WE#
BYTE#
RESET#
OE#
RY/BY#
VCC
GND
NC
PIN NAME
Address Input
Data Input/Output
Q15 (Word mode)/LSB addr(Byte mode)
Chip Enable Input
Write Enable Input
Word/Byte Selection input
Hardware Reset Pin/Sector Protect
Unlock
Output Enable Input
Ready/Busy Output
Power Supply Pin (2.7V~3.6V)
Ground Pin
Pin Not Connected Internally
MX29LV400C PIN CONFIGURATIONS
44 SOP(500 mil)
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
GND
OE#
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
MX29LV400C T/B
MX29LV400C T/B
P/N:PM1300
REV. 1.1, AUG. 17, 2006
2
MX29LV400C T/B
MX29LV800C T/B
MX29LV160C T/B
48-Ball CSP (Ball Pitch = 0.8 mm, Top View, Balls Facing Down, 6 x 8 mm)
6
A13
A12
A14
A15
A16
BYTE#
Q15/
A-1
GND
5
A9
A8
A10
A11
Q7
Q14
Q13
Q6
4
WE#
RE-
SET#
NC
NC
Q5
Q12
VCC
Q4
3
RY/
BY#
A7
NC
NC
NC
Q2
Q10
Q11
Q3
2
A17
A6
A5
Q0
Q8
Q9
Q1
1
A3
A4
A2
A1
A0
CE#
OE#
GND
A
B
C
D
E
F
G
H
48-Ball CSP (Balls Facing Down, 4 x 6 mm)
6
A2
A4
A6
A17
NC
NC
WE#
NC
A9
A11
5
A1
A3
A7
NC
NC
A10
A13
A14
4
A0
A5
NC
A8
A12
A15
3
CE#
Q8
Q10
Q4
Q11
A16
2
GND
OE#
Q9
NC
NC
Q5
Q6
Q7
1
Q0
Q1
Q2
Q3
VCC
Q12
Q13
Q14
Q15
GND
A
B
C
D
E
F
G
H
J
K
L
P/N:PM1300
REV. 1.1, AUG. 17, 2006
3
MX29LV400C T/B
MX29LV800C T/B
MX29LV160C T/B
MX29LV800C PIN CONFIGURATIONS
44 SOP(500 mil)
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
GND
OE#
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A18
Q0~Q14
Q15/A-1
CE#
WE#
BYTE#
RESET#
OE#
RY/BY#
VCC
GND
NC
Address Input
Data Input/Output
Q15(Word mode)/LSB addr(Byte mode)
Chip Enable Input
Write Enable Input
Word/Byte Selection input
Hardware Reset Pin
Output Enable Input
Ready/Busy Output
Power Supply Pin (2.7V~3.6V)
Ground Pin
Pin Not Connected Internally
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
MX29LV800CT/CB
MX29LV800CT/CB
P/N:PM1300
REV. 1.1, AUG. 17, 2006
4
MX29LV400C T/B
MX29LV800C T/B
MX29LV160C T/B
48-Ball CSP (Ball Pitch = 0.8 mm, Top View, Balls Facing Down, 6 x 8 mm)
6
A13
A12
A14
A15
A16
BYTE#
Q15/
A-1
GND
5
A9
A8
A10
A11
Q7
Q14
Q13
Q6
4
WE#
RE-
SET#
NC
NC
Q5
Q12
VCC
Q4
3
RY/
BY#
A7
NC
A18
NC
Q2
Q10
Q11
Q3
2
A17
A6
A5
Q0
Q8
Q9
Q1
1
A3
A4
A2
A1
A0
CE#
OE#
GND
A
B
C
D
E
F
G
H
48-Ball CSP (Balls Facing Down, 4 x 6 mm)
6
A2
A4
A6
A17
NC
NC
WE#
NC
A9
A11
5
A1
A3
A7
NC
NC
A10
A13
A14
4
A0
A5
A18
A8
A12
A15
3
CE#
Q8
Q10
Q4
Q11
A16
2
GND
OE#
Q9
NC
NC
Q5
Q6
Q7
1
Q0
Q1
Q2
Q3
VCC
Q12
Q13
Q14
Q15
GND
A
B
C
D
E
F
G
H
J
K
L
P/N:PM1300
REV. 1.1, AUG. 17, 2006
5
FPGA/CPLD
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