2.5V MULTI-QUEUE FIFO (4 QUEUES)
18 BIT WIDE CONFIGURATION
589,824 bits, 1,179,648 bits and
2,359,296 bits
ADVANCE INFORMATION
IDT72T51233
IDT72T51243
IDT72T51253
FEATURES:
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Choose from among the following memory density options:
IDT72T51233
Total Available Memory = 589,824 bits
IDT72T51243
Total Available Memory = 1,179,648 bits
IDT72T51253
Total Available Memory = 2,359,296 bits
Configurable from 1 to 4 Queues
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 512 x 18 or 1,024 x 9
Independent Read and Write access per queue
User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
User programmable via serial port
Default Multi-Queue device configurations
-IDT72T51233: 8,192 x 18 x 4Q
-IDT72T51243: 16,384 x 18 x 4Q
-IDT72T51253: 32,768 x 18 x 4Q
100% Bus Utilization, Read and Write on every clock cycle
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Echo Read Enable & Echo Read Clock Outputs
Individual, Active queue flags (OV,
FF, PAE, PAF, PR)
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4 bit parallel flag status on both read and write ports
Provides continuous
PAE
and
PAF
status of up to 4 Queues
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
- x18in to x18out
- x9in to x18out
- x18in to x9out
- x9in to x9out
FWFT mode of operation on read port
Packet Ready mode of operation
Partial Reset, clears data in single Queue
Expansion of up to 8 Multi-Queue devices in parallel is available
Power Down Input provides additional power savings in HSTL
and eHSTL modes.
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
DATA PATH FLOW DIAGRAM
MULTI-QUEUE FIFO
WADEN
FSTR
WRADD
WEN
WCLK
5
READ CONTROL
RADEN
ESTR
RDADD
6
WRITE CONTROL
Q0
REN
RCLK
EREN
ERCLK
OE
x9, x18
DATA IN
FF
PAF
PAFn
Din
Qout
x9, x18
DATA OUT
READ FLAGS
OV
PAE
PAEn
4
WRITE FLAGS
Qmax
4
6115 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2001
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
OCTOBER 2, 2001
DSC-6115/-
IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FIFO (4 QUEUES)
18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION:
The IDT72T51233/72T51243/72T51253 Multi-Queue FIFO device is a
single chip within which anywhere between 1 and 4 discrete FIFO queues
can be setup. All queues within the device have a common data input bus,
(write port) and a common data output bus, (read port). Data written into the
write port is directed to a respective queue via an internal de-multiplex
operation, addressed by the user. Data read from the read port is accessed
from a respective queue via an internal multiplex operation, addressed by
the user. Data writes and reads can be performed at high speeds up to
200MHz, with access times of 3.6ns. Data write and read operations are totally
independent of each other, a queue maybe selected on the write port and
a different queue on the read port or both ports may select the same queue
simultaneously.
The device provides Full flag and Output Valid flag status for the queue
selected for write and read operations respectively. Also a Programmable
Almost Full and Programmable Almost Empty flag for each queue is provided.
Two 4 bit programmable flag busses are available, providing status of all
queues, including queues not selected for write or read operations, these flag
busses provide an individual flag per queue.
Bus Matching is available on this device, either port can be 9 bits or 18 bits
wide. When Bus Matching is used the device ensures the logical transfer of
data throughput in a Little Endian manner.
The user has full flexibility configuring queues within the device, being able
to program the total number of queues between 1 and 4, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the Multi-Queue device, a default option is
available that configures the device in a predetermined manner.
Both Master Reset and Partial Reset pins are provided on this device. A Master
Reset latches in all configuration setup pins and must be performed before
programming of the device can take place. A Partial Reset will reset the read and
write pointers of an individual FIFO queue, provided that the queue is selected
on both the write port and read port at the time of partial reset.
Echo Read Enable,
EREN
and Echo Read Clock, ERCLK outputs are
provided. These are outputs from the read port of the FIFO that are required for
high speed data communication, to provide tighter synchronization between the
data being transmitted from the Qn outputs and the data being received by the
input device. Data read from the read port is available on the output bus with
respect to
EREN
and ERCLK, this is very useful when data is being read at high
speed.
The Multi-Queue FIFO has the capability of operating its IO in either 2.5V
LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected via the
IOSEL input. The core supply voltage (V
CC
) to the Multi-Queue is always 2.5V,
however the output levels can be set independently via a separate supply, V
DDQ
.
The devices also provide additional power savings via a Power Down Input.
This input disables the write port data inputs when no write operations are
required.
A JTAG test port is provided, here the Multi-Queue FIFO has a fully functional
Boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port
and Boundary Scan Architecture.
See Figure 1,
Multi-Queue FIFO Block Diagram
for an outline of the functional
blocks within the device.
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IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FIFO (4 QUEUES)
18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DETAILED DESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT Multi-Queue FIFO has a single data input port and single data output
port with up to 4 FIFO queues in parallel buffering between the two ports. The
user can setup between 1 and 4 FIFO Queues within the device. These queues
can be configured to utilize the total available memory, providing the user with
full flexibility and ability to configure the queues to be various depths, indepen-
dent of one another.
MEMORY ORGANIZATION/ ALLOCATION
The memory is organized into what is known as “blocks”, each block being
512 x 18 or 1,024 x 9 bits. When the user is configuring the number of queues
and individual queue sizes the user must allocate the memory to respective
queues, in units of blocks, that is, a single queue can be made up from 0 to m
blocks, where m is the total number of blocks available within a device. Also the
total size of any given queue must be in increments of 512 x 18 or 1,024 x 9.
For the IDT72T51233, IDT72T51243 and IDT72T51253 the Total Available
Memory is 64, 128 and 256 blocks respectively (a block being 512 x 18 or 1,024
x 9). If any port is configured for x18 bus width, a block size is 512 x 18. If both
the write and read ports are configured for x9 bus width, a block size is 1,024
x 9. Queues can be built from these blocks to make any size queue desired and
any number of queues desired.
BUS WIDTHS
The input port is common to all FIFO queues within the device, as is the output
port. The device provides the user with Bus Matching options such that the input
port and output port can be either x9 or x18 bits wide, the read and write port
widths being set independently of one another. Because the ports are common
to all queues the width of the queues is not individually set, so that the input width
of all queues are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Data being written into the device via the input port is directed to a discrete
FIFO queue via the write queue select address inputs. Conversely, data being
read from the device read port is read from a queue selected via the read queue
select address inputs. Data can be simultaneously written into and read from the
same FIFO queue or different FIFO queues. Once a queue is selected for data
writes or reads, the writing and reading operation is performed in the same
manner as conventional IDT synchronous FIFO’s, utilizing clocks and enables,
there is a single clock and enable per port. When a specific queue is addressed
on the write port, data placed on the data inputs is written to that queue
sequentially based on the rising edge of a write clock provided setup and hold
times are met. Conversely, data is read on to the output port after an access time
from a rising edge on a read clock.
The operation of the write port is comparable to the function of a conventional
FIFO operating in standard IDT mode. Write operations can be performed on
the write port provided that the queue currently selected is not full, a full flag output
provides status of the selected queue. The operation of the read port is
comparable to the function of a conventional FIFO operating in FWFT mode.
When a FIFO queue is selected on the output port, the next word in that queue
will automatically fall through to the output register. All subsequent words from
that queue require an enabled read cycle. Data cannot be read from a selected
queue if that queue is empty, the read port provides an Output Valid flag indicating
when data read out is valid. If the user switches to a queue that is empty, the
last word from the previous queue will remain on the output register.
As mentioned, the write port has a full flag, providing full status of the selected
queue. Along with the full flag a dedicated almost full flag is provided, this almost
full flag is similar to the almost full flag of a conventional IDT FIFO. The device
5
provides a user programmable almost full flag for all 4 FIFO queues and when
a respective queue is selected on the write port, the almost full flag provides status
for that queue. Conversely, the read port has an output valid flag, providing
status of the data being read from the queue selected on the read port. As well
as the output valid flag the device provides a dedicated almost empty flag. This
almost empty flag is similar to the almost empty flag of a conventional IDT FIFO.
The device provides a user programmable almost empty flag for all 4 FIFO
queues and when a respective queue is selected on the read port, the almost
empty flag provides status for that queue.
PROGRAMMABLE FLAG BUSSES
In addition to these dedicated flags, full & almost full on the write port and output
valid & almost empty on the read port, there are two flag status busses. An almost
full flag status bus is provided, this bus is 4 bits wide. Also, an almost empty flag
status bus is provided, again this bus is 4 bits wide. The purpose of these flag
busses is to provide the user with a means by which to monitor the data levels
within FIFO queues that may not be selected on the write or read port. As
mentioned, the device provides almost full and almost empty registers (program-
mable by the user) for each of the 4 FIFO queues in the device.
The 4 bit
PAEn
and 4 bit
PAFn
busses provide a discrete status of the Almost
Empty and Almost Full conditions of all 4 queue's. If the device is programmed
for less than 4 queue's, then there will be a corresponding number of active
outputs on the
PAEn
and
PAFn
busses.
The flag busses can provide a continuous status of all queues. If devices are
connected in expansion mode the individual flag busses can be left in a discrete
form, providing constant status of all queues, or the busses of individual devices
can be connected together to produce a single bus of 4 bits. The device can
then operate in a "Polled" or "Direct" mode.
When operating in polled mode the flag bus provides status of each device
sequentially, that is, on each rising edge of a clock the flag bus is updated to show
the status of each device in order. The rising edge of the write clock will update
the Almost Full bus and a rising edge on the read clock will update the Almost
Empty bus.
When operating in direct mode the device driving the flag bus is selected by
the user. The user addresses the device that will take control of a respective
flag bus, these
PAFn
and
PAEn
flag busses operating independently of one
another. Addressing of the Almost Full flag bus is done via the write port and
addressing of the Almost Empty flag bus is done via the read port.
EXPANSION
Expansion of Multi-Queue devices is also possible, up to 8 devices can be
connected in a parallel fashion providing the possibility of both depth expansion
or queue expansion. Depth Expansion means expanding the depths of
individual queues. Queue expansion means increasing the total number of
queues available. Depth expansion is possible by virtue of the fact that more
memory blocks within a Multi-Queue device can be allocated to increase the
depth of a queue. For example, depth expansion of 8 devices provides the
possibility of 8 queues of 32K x 18 deep within the IDT72T51233, 64K x 18 deep
within the IDT72T51243 and 128K x 18 deep within the IDT72T51253, each
queue being setup within a single device utilizing all memory blocks available
to produce a single queue. This is the deepest FIFO queue that can setup within
a device.
For queue expansion of the 4 queue device, a maximum number of 32 (8
x 4) queues may be setup, each queue being 4K x18 or 2K x 9 deep, if less
queues are setup, then more memory blocks will be available to increase queue
depths if desired. When connecting Multi-Queue devices in expansion mode
all respective input pins (data & control) and output pins (data & flags), should
be “connected” together between individual devices.
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