CAT5221
Dual Digital
Potentiometer (POT)
with 64 Taps
and I
2
C Interface
Description
http://onsemi.com
The CAT5221 is two digital POTs integrated with control logic and
16 bytes of NVRAM memory. Each digital POT consists of a series of
63 resistive elements connected between two externally accessible end
points. The tap points between each resistive element are connected to
the wiper outputs with CMOS switches. A separate 6-bit control
register (WCR) independently controls the wiper tap switches for each
digital POT. Associated with each wiper control register are four 6-bit
non-volatile memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or any of the
non-volatile data registers is via a I
2
C serial bus. On power-up, the
contents of the first data register (DR0) for each of the four
potentiometers is automatically loaded into its respective wiper
control register (WCR).
The CAT5221 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications.
Features
TSSOP−20
Y SUFFIX
CASE 948AQ
SOIC−20
W SUFFIX
CASE 751BJ
PIN CONNECTIONS
R
W0
R
L0
R
H0
A0
A2
R
W1
R
L1
R
H1
SDA
GND
SOIC−20 (W)
TSSOP−20 (Y)
(Top View)
CAT5221
1
V
CC
NC
NC
NC
A1
A3
SCL
NC
NC
NC
Two Linear-taper Digital Potentiometers
64 Resistor Taps per Potentiometer
End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW
Potentiometer Control and Memory Access via I
2
C Interface
Low Wiper Resistance, Typically 80
W
Nonvolatile Memory Storage for Up to Four Wiper Settings for Each
Potentiometer
Automatic Recall of Saved Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current less than 1
mA
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
20-lead SOIC and TSSOP Packages
Industrial Temperature Range
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013
−
Rev. 14
1
Publication Order Number:
CAT5221/D
CAT5221
MARKING DIAGRAMS
(SOIC−20)
L3B
CAT5221WT
−RRYMXXXX
(TSSOP−20)
RLB
CAT5221YI
3YMXXX
L = Assembly Location
3 = Lead Finish
−
Matte−Tin
B = Product Revision (Fixed as “B”)
CAT = Fixed a “CAT”
5221W = Device Code
T = Temperature Range
I = Industrial
A = Automobile
E = Extended
B = Leave blank if Commercial
−
= Dash
RR = Resistance
25 = 2.5 K Ohms
10 = 10 K Ohms
50 = 50 K Ohms
00 = 100 K Ohms
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXXX = Last Four Digits of Assembly Lot Number
R = Resistance
5 = 100 K Ohms
4 = 50 K Ohms
2 = 10 K Ohms
1 = 2.5 K Ohms
L = Assembly Location
B = Product Revision (Fixed as “B”)
CAT5221Y = Device Code
I = Temperature Range (I = Industrial)
3 = Lead Finish
−
Matte−Tin
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
R
H0
R
H1
SCL
SDA
I
2
C
INTERFACE
WIPER
CONTROL
REGISTERS
R
W0
R
W1
A0
A1
A2
A3
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R
L0
R
L1
Figure 1. Functional Diagram
http://onsemi.com
2
CAT5221
Table 1. PIN DESCRIPTION
Pin (SOIC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
R
W0
R
L0
R
H0
A0
A2
R
W1
R
L1
R
H1
SDA
GND
NC
NC
NC
SCL
A3
A1
NC
NC
NC
V
CC
Wiper Terminal for Potentiometer 0
Low Reference Terminal for Potentiometer 0
High Reference Terminal for Potentiometer 0
Device Address, LSB
Device Address
Wiper Terminal for Potentiometer 1
Low Reference Terminal for Potentiometer 1
High Reference Terminal for Potentiometer 1
Serial Data Input/Output
Ground
No Connect
No Connect
No Connect
Bus Serial Clock
Device Address
Device Address
No Connect
No Connect
No Connect
Supply Voltage
Function
PIN DESCRIPTION
SCL:
Serial Clock
The CAT5221 serial clock input pin is used to clock all
data transfers into or out of the device.
SDA:
Serial Data
The CAT5221 bidirectional serial data pin is used to
transfer data into and out of the device. The SDA pin is an
open drain output and can be wire-Or’d with the other open
drain or open collector outputs.
A0, A1, A2, A3:
Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of sixteen devices can be addressed
on a single bus. A match in the slave address must be made
with the address input in order to initiate communication
with the CAT5221.
R
H
, R
L
:
Resistor End Points
The two sets of R
H
and R
L
pins are equivalent to the
terminal connections on a mechanical potentiometer.
R
W
:
Wiper
The two R
W
pins are equivalent to the wiper terminal of
a mechanical potentiometer.
DEVICE OPERATION
The CAT5221 is two resistor arrays integrated with I
2
C
serial interface logic, two 6-bit wiper control registers and
eight 6-bit, non-volatile memory data registers. Each
resistor array contains 63 separate resistive elements
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
). R
H
and R
L
are symmetrical and
may be interchanged. The tap positions between and at the
ends of the series resistors are connected to the output wiper
terminals (R
W
) by a CMOS transistor switch. Only one tap
point for each potentiometer is connected to its wiper
terminal at a time and is determined by the value of the wiper
control register. Data can be read or written to the wiper
control registers or the non-volatile memory data registers
via the I
2
C bus. Additional instructions allow data to be
transferred between the wiper control registers and each
respective potentiometer’s non-volatile data registers. Also,
the device can be instructed to operate in an “increment/
decrement” mode.
http://onsemi.com
3
CAT5221
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to V
SS
(Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25C)
Lead Soldering Temperature (10 s)
Wiper Current
Ratings
−55
to +125
−65
to +150
−2.0
to +V
CC
+2.0
−2.0
to +7.0
1.0
300
12
Units
C
C
V
V
W
C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RECOMMENDED OPERATING CONDITIONS
(V
cc
= +2.5 V to +6 V)
Parameter
Operating Ambient Temperature (Industrial)
Ratings
−40
to +85
Units
C
Table 4. POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
R
POT
R
POT
R
POT
R
POT
Parameter
Potentiometer Resistance (−00)
Potentiometer Resistance (−50)
Potentiometer Resistance (−10)
Potentiometer Resistance (−2.5)
Potentiometer Resistance Tolerance
R
POT
Matching
Power Rating
I
W
R
W
R
W
V
TERM
V
N
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity (Note 4)
Relative Linearity (Note 5)
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
R
W(n)(actual)
−
R
(n)(expected)
(Note 7)
R
W(n+1)
−
[R
W(n)+LSB
]
(Note 7)
(Note 3)
(Note 3)
(Note 3)
R
POT
= 50 kW
10/10/25
0.4
300
20
I
W
= +3 mA @ V
CC
= 3 V
I
W
= +3 mA @ V
CC
= 5 V
V
SS
= 0 V
(Note 3)
GND
TBD
1.6
1
0.2
80
25C, each pot
Test Conditions
Min
Typ
100
50
10
2.5
20
1
50
6
300
150
V
CC
nV/Hz
%
LSB
(Note 6)
LSB
(Note 6)
ppm/C
ppm/C
pF
MHz
Max
Units
kW
kW
kW
kW
%
%
mW
mA
W
W
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V
CC
+ 1 V.
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
It is a measure of the error in step size.
6. LSB = R
TOT
/ 63 or (R
H
−
R
L
) / 63, single pot
7. n = 0, 1, 2, ..., 63
http://onsemi.com
4
CAT5221
Table 5. D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Standby Current (V
CC
= 5.0 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0 V)
I
OL
= 3 mA
Test Conditions
f
SCL
= 400 kHz
V
IN
= GND or V
CC
; SDA Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
−1
V
CC
x 0.7
Min
Typ
Max
1
1
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
Units
mA
mA
mA
mA
V
V
V
Table 6. CAPACITANCE
(T
A
= 25C, f = 1.0 MHz, V
CC
= 5 V)
Symbol
C
I/O
(Note 8)
C
IN
(Note 8)
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL)
Test Conditions
V
I/O
= 0 V
V
IN
= 0 V
Min
Typ
Max
8
6
Units
pF
pF
Table 7. A.C. CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
f
SCL
T
I
(Note 8)
t
AA
t
BUF
(Note 8)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 8)
t
F
(Note 8)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (For a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.6
50
1.2
0.6
1.2
0.6
0.6
0
100
0.3
300
Parameter
Min
Typ
Max
400
50
0.9
Units
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ns
ms
ns
ms
ns
Table 8. POWER UP TIMING
(Note 8) (Over recommended operating conditions unless otherwise stated.)
Symbol
t
PUR
t
PUW
Power-up to Read Operation
Power-up to Write Operation
Parameter
Min
Typ
Max
1
1
Units
ms
ms
8. This parameter is tested initially and after a design or process change that affects the parameter.
Table 9. WRITE CYCLE LIMITS
(Over recommended operating conditions unless otherwise stated.)
Symbol
t
WR
NOTE:
Parameter
Write Cycle Time
Min
Typ
Max
5
Units
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
http://onsemi.com
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
