CY28347
Universal Single-chip Clock Solution
for VIA P4M266/KM266 DDR Systems
Features
• Supports VIA P4M266/KM266 chipsets
• Supports Pentium
®
4, Athlon™ processors
• Supports two DDR DIMMS
• Provides
— Two different programmable CPU clock pairs
— Six differential DDR SDRAM pairs
— Two low-skew/low-jitter AGP clocks
— Six low-skew/low-jitter PCI clocks
— One 48M output for USB
— One programmable 24M or 48M for SIO
•
Dial-a-Frequency™ and Dial-a-dB™ features
• Spread Spectrum for best electromagnetic interference
(EMI) reduction
• SMBus-compatible for programmability
• 56-pin SSOP and TSSOP packages
Table 1. Frequency Selection Table
FS(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CPU
66.80
100.20
120.00
133.33
72.00
105.00
160.00
140.00
77.00
110.00
180.00
150.00
90.00
100.00
200.00
133.33
AGP
66.80
66.80
60.00
66.67
72.00
70.00
64.00
70.00
77.00
73.33
60.00
60.00
60.00
66.67
66.67
66.67
PCI
33.40
33.40
30.00
33.33
36.00
35.00
32.00
35.00
38.50
36.67
30.00
30.00
30.00
33.33
33.33
33.33
Block Diagram
XIN
XOUT
VDDR
XTAL
REF0
VDDI
SELP4_K7#
VDDC
REF(0:1)
CPUCS_T
CPUCS_C
CPUT/CPU0D_T
CPUC/CPU0D_C
PCI(3:5)
Pin Configuration
[1]
*FS0/REF0
VSSR
XIN
XOUT
VDDAGP
*MODE/AGP0
*SELP4_K7#/AGP1
*PCI_STP#
VSSAGP
**FS1/PCI_F
PCI1
*MULTSEL/PCI2
VSSPCI
PCI3
PCI4
VDDPCI
PCI5
*CPU_STP#
VSS48M
**FS3/48M
**FS2/24_48M
VDD48M
VDD
VSS
IREF
*PD#
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VTTPWRGD#/REF1
VDDR
VSSC
CPUT/CPUOD_T
CPUC/CPUOD_C
VDDC
VDDI
CPUCS_C
CPUCS_T
VSSI
FBOUT
BUF_IN
DDRT0
DDRC0
DDRT1
DDRC1
VDDD
VSSD
DDRT2
DDRC2
DDRT3
DDRC3
VDDD
VSSD
DDRT4
DDRC4
DDRT5
DDRC5
FS0
PCI_STP#
CPU_STP#
PD#
PLL1
FS2
VDDPCI
FS3 FS1
PCI_F
MULTSEL
PCI2
PCI1
AGP(0:1)
CY28347
VDDAGP
SDATA
SCLK
SMBus
PLL2
/2
VDD48M
48M
24_48M
SELSDR_DDR#
S2D
CONVERT
VDDD
FBOUT
DDRT(0:5)
DDRC(0:5)
BUF_IN
Note:
1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 21
www.SpectraLinear.com
CY28347
Pin Description
Pin
3
4
1
XIN
XOUT
FS0/REF0
VDD
VDD
[2]
Name
PWR
I/O
I
O
Description
Oscillator Buffer Input.
Connect to a crystal or to an external clock.
Oscillator Buffer Output.
Connect to a crystal. Do not connect when an external
clock is applied at XIN.
I/O
Power-on Bidirectional Input/Output.
At power-up, FS0 is the input. When the
PU power supply voltage crosses the input threshold voltage, FS0 state is latched and
this pin becomes REF0, buffered copy of signal applied at XIN. (1–2 x strength,
selectable by SMBus. Default value is 1 x strength.)
I
If SELP4_K7# = 1, with a P4 processor setup as CPU(T:C).
At power-up,
VTT_PWRGD# is an input. When this input is sampled LOW, the FS (3:0) and
MULTSEL are latched and all output clocks are enabled. After the first transition to
a LOW on VTT_PWRGD#, this pin is ignored and will not effect the behavior of the
device thereafter. When the VTT_PWRGD# feature is not used, please connect this
signal to ground through a 10KΩ resistor.
If SELP4_K7# = 0, with an Athlon (K7) processor as CPUOD_(T:C).
VTT_PWRGD# function is disabled, and the feature is ignored. This pin becomes
REF1 and is a buffered copy of the signal applied at XIN.
These pins are configured for DDR clock outputs.
They are “True” copies of
signal applied at Pin45, BUF_IN.
These pins are configured for DDR clock outputs.
They are “Complementary”
copies of signal applied at Pin45, BUF_IN.
56
VTTPWRGD#
VDDR
REF1
VDDR
O
44,42,38, DDRT(0:5)
36,32,30
43,41,37
35,31,29
7
DDRC(0:5)
SELP4_K7#/
AGP1
VDDD
VDDD
O
O
VDDAGP I/O
Power-on Bidirectional Input/Output.
At power-up, SELP4_K7# is the input.
PU When the power supply voltage crosses the input threshold voltage, SELP4_K7#
state is latched and this pin becomes AGP1 clock output. SELP4_K7# = 1 selects
P4 mode. SELP4_K7# = 0 selects K7 mode.
I/O
Power-on Bidirectional Input/Output.
At power-up, MULTSEL is the input. When
PU the power supply voltage crosses the input threshold voltage, MULTSEL state is
latched and this pin becomes PCI2 clock output. MULTSEL = 0, Ioh is 4 x
IREFMULTSEL = 1, Ioh is 6 x IREF
O
3.3V True CPU Clock Outputs.
This pin is programmable through strapping pin7,
SELP4_K7#. If SELP4_K7# = 1, this pin is configured as the CPUT Clock Output.
If SELP4_K7# = 0, this pin is configured as the CPUOD_T Open Drain Clock Output.
See
Table 1.
3.3V Complementary CPU Clock Outputs.
This pin is programmable through
strapping pin7, SELP4_K7#. If SELP4_K7# = 1, this pin is configured as the CPUC
Clock Output. If SELP4_K7# = 0, this pin is configured as the CPUOD_C Open
Drain Clock Output. See
Table 1.
PCI Clock Outputs.
Are synchronous to CPU clocks. See
Table 1.
2.5V CPU Clock Outputs for Chipset.
See
Table 1.
12
MULTSEL/PCI2 VDDPCI
53
CPUT/CPUOD_T
VDDC
52
CPUC/CPUOD_C
VDDC
O
14,15,17
48,49
18
PCI (3:5)
CPUCS_T/C
CPU_STP#
VDDPCI
VDDI
VDDPCI
O
O
I If pin 6 is pulled down at power on reset, then this pin becomes CPU_STP#. When
PU CPU_STP# is asserted LOW, then both of the CPU signals stop at the next HIGH
to LOW transition or stays LOW if it already is LOW. This does not stop the CPUCS
signals.
I/O
Power-on Bidirectional Input/Output.
At power-up, FS1 is the input. When the
PD power supply voltage crosses the input threshold voltage, FS1 state is latched and
this pin becomes PCI_F clock output.
10
FS1/PCI_F
VDDPCI
20
FS3/48M
VDD48M I/O
Power-on Bidirectional Input/Output.
At power-up, FS3 is the input. When the
PD power supply voltage crosses the input threshold voltage, FS3 state is latched and
this pin becomes 48M, a USB clock output.
VDDPCI
O
PCI Clock Output.
VDD48M I/O
Power-on Bidirectional Input/Output.
At power-up, FS2 is the input. When the
PD power supply voltage crosses the input threshold voltage, FS2 state is latched and
this pin becomes 24_48M, a SIO programmable clock output.
11
21
PCI1
FS2/24_48M
Note:
2. PU = internal pull-up. PD = internal pull-down. Typically = 250 kΩ (range 200 kΩ to 500 kΩ).
Rev 1.0, November 20, 2006
Page 2 of 21
CY28347
Pin Description
(continued)
[2]
Pin
6
Name
MODE/AGP0
PWR
I/O
Description
VDDAGP I/O
Power-on Bidirectional Input/Output.
At power-up, MODE is an input and
PU becomes AGP0 output after the power supply voltage crosses the input threshold
voltage. Must have 10KΩ resistor to V
SS
. See
Table 2.
VDDAGP
I
If pin 6 is pulled down at power on reset, then this pin becomes PCI_STP#.
PU When PCI_STP# is asserted LOW, then all of the PCI signals, except the PCI_F,
stops at the next HIGH to LOW transition or stays LOW if it already is LOW.
I
Current reference programming input for CPU buffers.
A precise resistor is
attached to this pin, which is connected to the internal current reference.
8
PCI_STP#
25
28
IREF
SDATA
I/O
Serial Data Input.
Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open drain output
when acknowledging or transmitting data.
I
Serial Clock Input.
Conforms to the SMBus specification.
I
When PD# is asserted LOW,
the device enters power down mode. See power
PU management function.
I
O
2.5V CMOS type input to the DDR differential buffers.
This is the single-ended, SDRAM buffered output of the signal applied at
BUF_IN.
It is in phase with the DDRT(0:5) signals.
3.3V power supply for AGP clocks.
3.3V power supply for CPU (T: C) clocks.
3.3V power supply for PCI clocks.
3.3V power supply for REF clock.
2.5V power supply for CPUCS_T/C clocks.
3.3V power supply for 48M.
3.3V Common power supply.
2.5V power supply for DDR clocks.
Ground for AGP clocks.
Ground for PCI clocks.
Ground for CPU (T:C) clocks.
Ground for DDR clocks.
Ground for 48M clock.
Ground for CPUCS_T/C clocks.
Common ground.
27
26
45
46
5
51
16
55
50
22
23
34,40
9
13
54
33,39
19
47
24
SCLK
PD#
BUF_IN
FBOUT
VDDAGP
VDDC
VDDPCI
VDDR
VDDI
VDD48M
VDD
VDDD
VSSAGP
VSSPCI
VSSC
VSSD
VSS48M
VSSI
VSS
Table 2. MODE Pin-Power Management Input Control
MODE, Pin 6
(Latched Input)
0
Invalid
Pin 26
PD#
Reserved
Board Target
Trace/Term Z
50 Ohm
50 Ohm
CPU_STP#
Reserved
Reference R,
IREF = VDD/(3*Rr)
Rr = 221 1%,
IREF = 5.00 mA
Rr = 475 1%,
IREF = 2.32 mA
Pin 18
PCI_STP#
Reserved
Pin 8
Table 3. Swing Select Functions Through Hardware
MULTSEL
0
1
Output Current
IOH = 4* Iref
IOH = 6* Iref
VOH@Z
1.0V@50
0.7V@50
Rev 1.0, November 20, 2006
Page 3 of 21
CY28347
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc., can be individually enabled or
disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Table 4. Command Code Definition
Bit
7
(6:0)
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits
should be “0000000”
Description
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write, and Block Read operation from the controller. For
Block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For Byte Write and Byte Read operations,
the system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 4.
The Block Write and Block Read protocol is outlined in
Table 5
while
Table 6
outlines the corresponding Byte Write and Byte
Read protocol. The slave receiver address is 11010010 (D2H).
Table 5. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
Description
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 Bit “00000000” stands for block
operation
Acknowledge from slave
Byte Count - 8 bits
Acknowledge from slave
Data byte 0 - 8 bits
Acknowledge from slave
Data byte 1 - 8 bits
Acknowledge from slave
Data Byte N/Slave Acknowledge...
Data Byte N - 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
....
Table 6. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
Description
Start
Slave address - 7 bits
Write
Bit
1
2:8
9
Byte Read Protocol
Description
Start
Slave address - 7 bits
Write
Block Read Protocol
Description
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 Bit “00000000” stands for block
operation
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Byte count from slave - 8 bits
Acknowledge
Data byte from slave - 8 bits
Acknowledge
Data byte from slave - 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave - 8 bits
Not Acknowledge
Stop
Rev 1.0, November 20, 2006
Page 4 of 21
CY28347
Table 6. Byte Read and Byte Write Protocol
(continued)
10
11:18
Acknowledge from slave
Command Code - 8 bits “1xxxxxxx” stands for byte
operation bit[6:0] of the command code represents
the offset of the byte to be accessed
Acknowledge from slave
Data Byte from Master – 8 Bits
Acknowledge from slave
Stop
10
11:18
Acknowledge from slave
Command Code - 8 bits “1xxxxxxx” stands for byte
operation bit[6:0] of the command code represents
the offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Data byte from slave - 8 bits
Not Acknowledge
Stop
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Byte 0: Frequency Select Register
Bit
7
6
5
4
3
@Pup
0
H/W Setting
H/W Setting
H/W Setting
0
21
10
1
FS2
FS1
FS0
Pin#
Name
Reserved.
For Selecting Frequencies see
Table 1.
For Selecting Frequencies see
Table 1.
For Selecting Frequencies see
Table 1.
If this bit is programmed to “1,” it enables WRITES to bits (6:4,1) for
selecting the frequency via software (SMBus)
If this bit is programmed to a “0” it enables only READS of bits
(6:4,1), which reflect the hardware setting of FS(0:3).
11
20
7
Reserved
FS3
SELP4_K7#
Reserved
For Selecting frequencies in
Table 1.
Only for reading the hardware setting of the CPU interface mode,
status of SELP4_K7# strapping.
Description
2
1
0
H/W Setting
H/W Setting
H/W Setting
Byte 1: CPU Clocks Register
Bit
7
6
5
4
3
2
1
@Pup
0
1
1
1
1
1
0
48,49
53,52
53,52
Pin#
Name
SSMODE
SSCG
SST1
SST0
CPUCS_T/C_ EN#
CPUOD_T/C_EN#
CPUT/C_PD_CNTRL
Description
0 = Down Spread. 1 = Center Spread. See
Table 10.
1 = Enable (default). 0 = Disable
Select spread bandwidth. See
Table 10.
Select spread bandwidth. See
Table 10.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
1 = output enabled (running). 0 = output disable asynchronously
in a LOW state.
In K7 mode, this bit is ignored. In P4 mode, when PD# asserted
LOW, 0 = drive CPUT to 2xIref and CPUC LOW and
1 = three-state CPUT and CPUC.
Only For reading the hardware setting of the Pin11 MULT0 value.
0
1
11
MULT0
Byte 2: PCI Clock Register
Bit
7
6
5
@Pup
0
1
1
10
Pin#
Name
PCI_DRV
PCI_F
Description
PCI clock output drive strength 0 = Normal, 1 = increase the drive
strength 20%.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
Reserved, set = 1.
Rev 1.0, November 20, 2006
Page 5 of 21
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